/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2023-10-23     RealThread   first version
 */

#ifndef __BOARD_H__
#define __BOARD_H__

#include <stm32f4xx_hal.h>

#ifdef __cplusplus
extern "C" {
#endif

/* STM32F407VE: 512KB Flash, 128KB SRAM + 64KB CCM RAM */
#define STM32_FLASH_START_ADRESS       ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE               (512 * 1024)
#define STM32_FLASH_END_ADDRESS        (STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)

#define STM32_SRAM1_START              (0x20000000)
#define STM32_SRAM1_SIZE               (128 * 1024)
#define STM32_SRAM1_END                (STM32_SRAM1_START + STM32_SRAM1_SIZE)

#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN      (__segment_end("CSTACK"))
#else
extern int __heap_start__;
#define HEAP_BEGIN      ((void *)&__heap_start__)
#endif

#define HEAP_END        STM32_SRAM1_END

void SystemClock_Config(void);

#ifdef __cplusplus
}
#endif

#endif