stm32_project/stm32f4_makefile
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

初始版本

Browse Source
This commit is contained in:
冯佳
2025-06-25 11:12:18 +08:00
parent db5c55af45
commit 8a2b0e21ee
1503 changed files with 1163734 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

323
build/gpio.lst Normal file
View File

@ -0,0 +1,323 @@
ARM GAS /tmp/ccVuJrQ5.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "gpio.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_GPIO_Init,"ax",%progbits
20 .align 1
21 .global MX_GPIO_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_GPIO_Init:
27 .LFB134:
28 .file 1 "Src/gpio.c"
1:Src/gpio.c **** /* USER CODE BEGIN Header */
2:Src/gpio.c **** /**
3:Src/gpio.c **** ******************************************************************************
4:Src/gpio.c **** * @file gpio.c
5:Src/gpio.c **** * @brief This file provides code for the configuration
6:Src/gpio.c **** * of all used GPIO pins.
7:Src/gpio.c **** ******************************************************************************
8:Src/gpio.c **** * @attention
9:Src/gpio.c **** *
10:Src/gpio.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/gpio.c **** * All rights reserved.
12:Src/gpio.c **** *
13:Src/gpio.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/gpio.c **** * in the root directory of this software component.
15:Src/gpio.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/gpio.c **** *
17:Src/gpio.c **** ******************************************************************************
18:Src/gpio.c **** */
19:Src/gpio.c **** /* USER CODE END Header */
20:Src/gpio.c ****
21:Src/gpio.c **** /* Includes ------------------------------------------------------------------*/
22:Src/gpio.c **** #include "gpio.h"
23:Src/gpio.c ****
24:Src/gpio.c **** /* USER CODE BEGIN 0 */
25:Src/gpio.c ****
26:Src/gpio.c **** /* USER CODE END 0 */
27:Src/gpio.c ****
28:Src/gpio.c **** /*----------------------------------------------------------------------------*/
29:Src/gpio.c **** /* Configure GPIO */
30:Src/gpio.c **** /*----------------------------------------------------------------------------*/
ARM GAS /tmp/ccVuJrQ5.s page 2
31:Src/gpio.c **** /* USER CODE BEGIN 1 */
32:Src/gpio.c ****
33:Src/gpio.c **** /* USER CODE END 1 */
34:Src/gpio.c ****
35:Src/gpio.c **** /** Configure pins as
36:Src/gpio.c **** * Analog
37:Src/gpio.c **** * Input
38:Src/gpio.c **** * Output
39:Src/gpio.c **** * EVENT_OUT
40:Src/gpio.c **** * EXTI
41:Src/gpio.c **** PD0 ------> CAN1_RX
42:Src/gpio.c **** */
43:Src/gpio.c **** void MX_GPIO_Init(void)
44:Src/gpio.c **** {
29 .loc 1 44 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 40
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 70B5 push {r4, r5, r6, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 16
36 .cfi_offset 4, -16
37 .cfi_offset 5, -12
38 .cfi_offset 6, -8
39 .cfi_offset 14, -4
40 0002 8AB0 sub sp, sp, #40
41 .LCFI1:
42 .cfi_def_cfa_offset 56
45:Src/gpio.c ****
46:Src/gpio.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
43 .loc 1 46 3 view .LVU1
44 .loc 1 46 20 is_stmt 0 view .LVU2
45 0004 0024 movs r4, #0
46 0006 0594 str r4, [sp, #20]
47 0008 0694 str r4, [sp, #24]
48 000a 0794 str r4, [sp, #28]
49 000c 0894 str r4, [sp, #32]
50 000e 0994 str r4, [sp, #36]
47:Src/gpio.c ****
48:Src/gpio.c **** /* GPIO Ports Clock Enable */
49:Src/gpio.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
51 .loc 1 49 3 is_stmt 1 view .LVU3
52 .LBB2:
53 .loc 1 49 3 view .LVU4
54 0010 0094 str r4, [sp]
55 .loc 1 49 3 view .LVU5
56 0012 2C4B ldr r3, .L3
57 0014 1A6B ldr r2, [r3, #48]
58 0016 42F00402 orr r2, r2, #4
59 001a 1A63 str r2, [r3, #48]
60 .loc 1 49 3 view .LVU6
61 001c 1A6B ldr r2, [r3, #48]
62 001e 02F00402 and r2, r2, #4
63 0022 0092 str r2, [sp]
64 .loc 1 49 3 view .LVU7
65 0024 009A ldr r2, [sp]
66 .LBE2:
ARM GAS /tmp/ccVuJrQ5.s page 3
67 .loc 1 49 3 view .LVU8
50:Src/gpio.c **** __HAL_RCC_GPIOH_CLK_ENABLE();
68 .loc 1 50 3 view .LVU9
69 .LBB3:
70 .loc 1 50 3 view .LVU10
71 0026 0194 str r4, [sp, #4]
72 .loc 1 50 3 view .LVU11
73 0028 1A6B ldr r2, [r3, #48]
74 002a 42F08002 orr r2, r2, #128
75 002e 1A63 str r2, [r3, #48]
76 .loc 1 50 3 view .LVU12
77 0030 1A6B ldr r2, [r3, #48]
78 0032 02F08002 and r2, r2, #128
79 0036 0192 str r2, [sp, #4]
80 .loc 1 50 3 view .LVU13
81 0038 019A ldr r2, [sp, #4]
82 .LBE3:
83 .loc 1 50 3 view .LVU14
51:Src/gpio.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
84 .loc 1 51 3 view .LVU15
85 .LBB4:
86 .loc 1 51 3 view .LVU16
87 003a 0294 str r4, [sp, #8]
88 .loc 1 51 3 view .LVU17
89 003c 1A6B ldr r2, [r3, #48]
90 003e 42F00202 orr r2, r2, #2
91 0042 1A63 str r2, [r3, #48]
92 .loc 1 51 3 view .LVU18
93 0044 1A6B ldr r2, [r3, #48]
94 0046 02F00202 and r2, r2, #2
95 004a 0292 str r2, [sp, #8]
96 .loc 1 51 3 view .LVU19
97 004c 029A ldr r2, [sp, #8]
98 .LBE4:
99 .loc 1 51 3 view .LVU20
52:Src/gpio.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
100 .loc 1 52 3 view .LVU21
101 .LBB5:
102 .loc 1 52 3 view .LVU22
103 004e 0394 str r4, [sp, #12]
104 .loc 1 52 3 view .LVU23
105 0050 1A6B ldr r2, [r3, #48]
106 0052 42F00102 orr r2, r2, #1
107 0056 1A63 str r2, [r3, #48]
108 .loc 1 52 3 view .LVU24
109 0058 1A6B ldr r2, [r3, #48]
110 005a 02F00102 and r2, r2, #1
111 005e 0392 str r2, [sp, #12]
112 .loc 1 52 3 view .LVU25
113 0060 039A ldr r2, [sp, #12]
114 .LBE5:
115 .loc 1 52 3 view .LVU26
53:Src/gpio.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
116 .loc 1 53 3 view .LVU27
117 .LBB6:
118 .loc 1 53 3 view .LVU28
119 0062 0494 str r4, [sp, #16]
ARM GAS /tmp/ccVuJrQ5.s page 4
120 .loc 1 53 3 view .LVU29
121 0064 1A6B ldr r2, [r3, #48]
122 0066 42F00802 orr r2, r2, #8
123 006a 1A63 str r2, [r3, #48]
124 .loc 1 53 3 view .LVU30
125 006c 1B6B ldr r3, [r3, #48]
126 006e 03F00803 and r3, r3, #8
127 0072 0493 str r3, [sp, #16]
128 .loc 1 53 3 view .LVU31
129 0074 049B ldr r3, [sp, #16]
130 .LBE6:
131 .loc 1 53 3 view .LVU32
54:Src/gpio.c ****
55:Src/gpio.c **** /*Configure GPIO pin Output Level */
56:Src/gpio.c **** HAL_GPIO_WritePin(SPI_FLASH_CS_GPIO_Port, SPI_FLASH_CS_Pin, GPIO_PIN_RESET);
132 .loc 1 56 3 view .LVU33
133 0076 144E ldr r6, .L3+4
134 0078 2246 mov r2, r4
135 007a 0121 movs r1, #1
136 007c 3046 mov r0, r6
137 007e FFF7FEFF bl HAL_GPIO_WritePin
138 .LVL0:
57:Src/gpio.c ****
58:Src/gpio.c **** /*Configure GPIO pin : SPI_FLASH_CS_Pin */
59:Src/gpio.c **** GPIO_InitStruct.Pin = SPI_FLASH_CS_Pin;
139 .loc 1 59 3 view .LVU34
140 .loc 1 59 23 is_stmt 0 view .LVU35
141 0082 0125 movs r5, #1
142 0084 0595 str r5, [sp, #20]
60:Src/gpio.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
143 .loc 1 60 3 is_stmt 1 view .LVU36
144 .loc 1 60 24 is_stmt 0 view .LVU37
145 0086 0695 str r5, [sp, #24]
61:Src/gpio.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
146 .loc 1 61 3 is_stmt 1 view .LVU38
147 .loc 1 61 24 is_stmt 0 view .LVU39
148 0088 0794 str r4, [sp, #28]
62:Src/gpio.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
149 .loc 1 62 3 is_stmt 1 view .LVU40
150 .loc 1 62 25 is_stmt 0 view .LVU41
151 008a 0894 str r4, [sp, #32]
63:Src/gpio.c **** HAL_GPIO_Init(SPI_FLASH_CS_GPIO_Port, &GPIO_InitStruct);
152 .loc 1 63 3 is_stmt 1 view .LVU42
153 008c 05A9 add r1, sp, #20
154 008e 3046 mov r0, r6
155 0090 FFF7FEFF bl HAL_GPIO_Init
156 .LVL1:
64:Src/gpio.c ****
65:Src/gpio.c **** /*Configure GPIO pin : PD0 */
66:Src/gpio.c **** GPIO_InitStruct.Pin = GPIO_PIN_0;
157 .loc 1 66 3 view .LVU43
158 .loc 1 66 23 is_stmt 0 view .LVU44
159 0094 0595 str r5, [sp, #20]
67:Src/gpio.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
160 .loc 1 67 3 is_stmt 1 view .LVU45
161 .loc 1 67 24 is_stmt 0 view .LVU46
162 0096 0223 movs r3, #2
ARM GAS /tmp/ccVuJrQ5.s page 5
163 0098 0693 str r3, [sp, #24]
68:Src/gpio.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
164 .loc 1 68 3 is_stmt 1 view .LVU47
165 .loc 1 68 24 is_stmt 0 view .LVU48
166 009a 0794 str r4, [sp, #28]
69:Src/gpio.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
167 .loc 1 69 3 is_stmt 1 view .LVU49
168 .loc 1 69 25 is_stmt 0 view .LVU50
169 009c 0323 movs r3, #3
170 009e 0893 str r3, [sp, #32]
70:Src/gpio.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
171 .loc 1 70 3 is_stmt 1 view .LVU51
172 .loc 1 70 29 is_stmt 0 view .LVU52
173 00a0 0923 movs r3, #9
174 00a2 0993 str r3, [sp, #36]
71:Src/gpio.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
175 .loc 1 71 3 is_stmt 1 view .LVU53
176 00a4 094D ldr r5, .L3+8
177 00a6 05A9 add r1, sp, #20
178 00a8 2846 mov r0, r5
179 00aa FFF7FEFF bl HAL_GPIO_Init
180 .LVL2:
72:Src/gpio.c ****
73:Src/gpio.c **** /*Configure GPIO pin : SD_CARD_DET_Pin */
74:Src/gpio.c **** GPIO_InitStruct.Pin = SD_CARD_DET_Pin;
181 .loc 1 74 3 view .LVU54
182 .loc 1 74 23 is_stmt 0 view .LVU55
183 00ae 0823 movs r3, #8
184 00b0 0593 str r3, [sp, #20]
75:Src/gpio.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
185 .loc 1 75 3 is_stmt 1 view .LVU56
186 .loc 1 75 24 is_stmt 0 view .LVU57
187 00b2 0694 str r4, [sp, #24]
76:Src/gpio.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
188 .loc 1 76 3 is_stmt 1 view .LVU58
189 .loc 1 76 24 is_stmt 0 view .LVU59
190 00b4 0794 str r4, [sp, #28]
77:Src/gpio.c **** HAL_GPIO_Init(SD_CARD_DET_GPIO_Port, &GPIO_InitStruct);
191 .loc 1 77 3 is_stmt 1 view .LVU60
192 00b6 05A9 add r1, sp, #20
193 00b8 2846 mov r0, r5
194 00ba FFF7FEFF bl HAL_GPIO_Init
195 .LVL3:
78:Src/gpio.c ****
79:Src/gpio.c **** }
196 .loc 1 79 1 is_stmt 0 view .LVU61
197 00be 0AB0 add sp, sp, #40
198 .LCFI2:
199 .cfi_def_cfa_offset 16
200 @ sp needed
201 00c0 70BD pop {r4, r5, r6, pc}
202 .L4:
203 00c2 00BF .align 2
204 .L3:
205 00c4 00380240 .word 1073887232
206 00c8 00040240 .word 1073873920
207 00cc 000C0240 .word 1073875968
ARM GAS /tmp/ccVuJrQ5.s page 6
208 .cfi_endproc
209 .LFE134:
211 .text
212 .Letext0:
213 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
214 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
215 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
216 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
ARM GAS /tmp/ccVuJrQ5.s page 7
DEFINED SYMBOLS
*ABS*:0000000000000000 gpio.c
/tmp/ccVuJrQ5.s:20 .text.MX_GPIO_Init:0000000000000000 $t
/tmp/ccVuJrQ5.s:26 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init
/tmp/ccVuJrQ5.s:205 .text.MX_GPIO_Init:00000000000000c4 $d
UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init

163
build/iwdg.lst Normal file
View File

@ -0,0 +1,163 @@
ARM GAS /tmp/ccABLkem.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "iwdg.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_IWDG_Init,"ax",%progbits
20 .align 1
21 .global MX_IWDG_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_IWDG_Init:
27 .LFB134:
28 .file 1 "Src/iwdg.c"
1:Src/iwdg.c **** /* USER CODE BEGIN Header */
2:Src/iwdg.c **** /**
3:Src/iwdg.c **** ******************************************************************************
4:Src/iwdg.c **** * @file iwdg.c
5:Src/iwdg.c **** * @brief This file provides code for the configuration
6:Src/iwdg.c **** * of the IWDG instances.
7:Src/iwdg.c **** ******************************************************************************
8:Src/iwdg.c **** * @attention
9:Src/iwdg.c **** *
10:Src/iwdg.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/iwdg.c **** * All rights reserved.
12:Src/iwdg.c **** *
13:Src/iwdg.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/iwdg.c **** * in the root directory of this software component.
15:Src/iwdg.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/iwdg.c **** *
17:Src/iwdg.c **** ******************************************************************************
18:Src/iwdg.c **** */
19:Src/iwdg.c **** /* USER CODE END Header */
20:Src/iwdg.c **** /* Includes ------------------------------------------------------------------*/
21:Src/iwdg.c **** #include "iwdg.h"
22:Src/iwdg.c ****
23:Src/iwdg.c **** /* USER CODE BEGIN 0 */
24:Src/iwdg.c ****
25:Src/iwdg.c **** /* USER CODE END 0 */
26:Src/iwdg.c ****
27:Src/iwdg.c **** IWDG_HandleTypeDef hiwdg;
28:Src/iwdg.c ****
29:Src/iwdg.c **** /* IWDG init function */
30:Src/iwdg.c **** void MX_IWDG_Init(void)
ARM GAS /tmp/ccABLkem.s page 2
31:Src/iwdg.c **** {
29 .loc 1 31 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 08B5 push {r3, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
32:Src/iwdg.c ****
33:Src/iwdg.c **** /* USER CODE BEGIN IWDG_Init 0 */
34:Src/iwdg.c ****
35:Src/iwdg.c **** /* USER CODE END IWDG_Init 0 */
36:Src/iwdg.c ****
37:Src/iwdg.c **** /* USER CODE BEGIN IWDG_Init 1 */
38:Src/iwdg.c ****
39:Src/iwdg.c **** /* USER CODE END IWDG_Init 1 */
40:Src/iwdg.c **** hiwdg.Instance = IWDG;
38 .loc 1 40 3 view .LVU1
39 .loc 1 40 18 is_stmt 0 view .LVU2
40 0002 0748 ldr r0, .L5
41 0004 074B ldr r3, .L5+4
42 0006 0360 str r3, [r0]
41:Src/iwdg.c **** hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
43 .loc 1 41 3 is_stmt 1 view .LVU3
44 .loc 1 41 24 is_stmt 0 view .LVU4
45 0008 0023 movs r3, #0
46 000a 4360 str r3, [r0, #4]
42:Src/iwdg.c **** hiwdg.Init.Reload = 4095;
47 .loc 1 42 3 is_stmt 1 view .LVU5
48 .loc 1 42 21 is_stmt 0 view .LVU6
49 000c 40F6FF73 movw r3, #4095
50 0010 8360 str r3, [r0, #8]
43:Src/iwdg.c **** if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
51 .loc 1 43 3 is_stmt 1 view .LVU7
52 .loc 1 43 7 is_stmt 0 view .LVU8
53 0012 FFF7FEFF bl HAL_IWDG_Init
54 .LVL0:
55 .loc 1 43 6 view .LVU9
56 0016 00B9 cbnz r0, .L4
57 .L1:
44:Src/iwdg.c **** {
45:Src/iwdg.c **** Error_Handler();
46:Src/iwdg.c **** }
47:Src/iwdg.c **** /* USER CODE BEGIN IWDG_Init 2 */
48:Src/iwdg.c ****
49:Src/iwdg.c **** /* USER CODE END IWDG_Init 2 */
50:Src/iwdg.c ****
51:Src/iwdg.c **** }
58 .loc 1 51 1 view .LVU10
59 0018 08BD pop {r3, pc}
60 .L4:
45:Src/iwdg.c **** }
61 .loc 1 45 5 is_stmt 1 view .LVU11
62 001a FFF7FEFF bl Error_Handler
63 .LVL1:
ARM GAS /tmp/ccABLkem.s page 3
64 .loc 1 51 1 is_stmt 0 view .LVU12
65 001e FBE7 b .L1
66 .L6:
67 .align 2
68 .L5:
69 0020 00000000 .word .LANCHOR0
70 0024 00300040 .word 1073754112
71 .cfi_endproc
72 .LFE134:
74 .global hiwdg
75 .section .bss.hiwdg,"aw",%nobits
76 .align 2
77 .set .LANCHOR0,. + 0
80 hiwdg:
81 0000 00000000 .space 12
81 00000000
81 00000000
82 .text
83 .Letext0:
84 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
85 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
86 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
87 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h"
88 .file 6 "Inc/main.h"
89 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
90 .file 8 "Inc/iwdg.h"
ARM GAS /tmp/ccABLkem.s page 4
DEFINED SYMBOLS
*ABS*:0000000000000000 iwdg.c
/tmp/ccABLkem.s:20 .text.MX_IWDG_Init:0000000000000000 $t
/tmp/ccABLkem.s:26 .text.MX_IWDG_Init:0000000000000000 MX_IWDG_Init
/tmp/ccABLkem.s:69 .text.MX_IWDG_Init:0000000000000020 $d
/tmp/ccABLkem.s:80 .bss.hiwdg:0000000000000000 hiwdg
/tmp/ccABLkem.s:76 .bss.hiwdg:0000000000000000 $d
UNDEFINED SYMBOLS
HAL_IWDG_Init
Error_Handler

1681
build/main.lst Normal file
View File

File diff suppressed because it is too large Load Diff

297
build/rng.lst Normal file
View File

@ -0,0 +1,297 @@
ARM GAS /tmp/cc62HSfH.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "rng.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_RNG_Init,"ax",%progbits
20 .align 1
21 .global MX_RNG_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_RNG_Init:
27 .LFB134:
28 .file 1 "Src/rng.c"
1:Src/rng.c **** /* USER CODE BEGIN Header */
2:Src/rng.c **** /**
3:Src/rng.c **** ******************************************************************************
4:Src/rng.c **** * @file rng.c
5:Src/rng.c **** * @brief This file provides code for the configuration
6:Src/rng.c **** * of the RNG instances.
7:Src/rng.c **** ******************************************************************************
8:Src/rng.c **** * @attention
9:Src/rng.c **** *
10:Src/rng.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/rng.c **** * All rights reserved.
12:Src/rng.c **** *
13:Src/rng.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/rng.c **** * in the root directory of this software component.
15:Src/rng.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/rng.c **** *
17:Src/rng.c **** ******************************************************************************
18:Src/rng.c **** */
19:Src/rng.c **** /* USER CODE END Header */
20:Src/rng.c **** /* Includes ------------------------------------------------------------------*/
21:Src/rng.c **** #include "rng.h"
22:Src/rng.c ****
23:Src/rng.c **** /* USER CODE BEGIN 0 */
24:Src/rng.c ****
25:Src/rng.c **** /* USER CODE END 0 */
26:Src/rng.c ****
27:Src/rng.c **** RNG_HandleTypeDef hrng;
28:Src/rng.c ****
29:Src/rng.c **** /* RNG init function */
30:Src/rng.c **** void MX_RNG_Init(void)
ARM GAS /tmp/cc62HSfH.s page 2
31:Src/rng.c **** {
29 .loc 1 31 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 08B5 push {r3, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
32:Src/rng.c ****
33:Src/rng.c **** /* USER CODE BEGIN RNG_Init 0 */
34:Src/rng.c ****
35:Src/rng.c **** /* USER CODE END RNG_Init 0 */
36:Src/rng.c ****
37:Src/rng.c **** /* USER CODE BEGIN RNG_Init 1 */
38:Src/rng.c ****
39:Src/rng.c **** /* USER CODE END RNG_Init 1 */
40:Src/rng.c **** hrng.Instance = RNG;
38 .loc 1 40 3 view .LVU1
39 .loc 1 40 17 is_stmt 0 view .LVU2
40 0002 0548 ldr r0, .L5
41 0004 054B ldr r3, .L5+4
42 0006 0360 str r3, [r0]
41:Src/rng.c **** if (HAL_RNG_Init(&hrng) != HAL_OK)
43 .loc 1 41 3 is_stmt 1 view .LVU3
44 .loc 1 41 7 is_stmt 0 view .LVU4
45 0008 FFF7FEFF bl HAL_RNG_Init
46 .LVL0:
47 .loc 1 41 6 view .LVU5
48 000c 00B9 cbnz r0, .L4
49 .L1:
42:Src/rng.c **** {
43:Src/rng.c **** Error_Handler();
44:Src/rng.c **** }
45:Src/rng.c **** /* USER CODE BEGIN RNG_Init 2 */
46:Src/rng.c ****
47:Src/rng.c **** /* USER CODE END RNG_Init 2 */
48:Src/rng.c ****
49:Src/rng.c **** }
50 .loc 1 49 1 view .LVU6
51 000e 08BD pop {r3, pc}
52 .L4:
43:Src/rng.c **** }
53 .loc 1 43 5 is_stmt 1 view .LVU7
54 0010 FFF7FEFF bl Error_Handler
55 .LVL1:
56 .loc 1 49 1 is_stmt 0 view .LVU8
57 0014 FBE7 b .L1
58 .L6:
59 0016 00BF .align 2
60 .L5:
61 0018 00000000 .word .LANCHOR0
62 001c 00080650 .word 1342572544
63 .cfi_endproc
64 .LFE134:
66 .section .text.HAL_RNG_MspInit,"ax",%progbits
ARM GAS /tmp/cc62HSfH.s page 3
67 .align 1
68 .global HAL_RNG_MspInit
69 .syntax unified
70 .thumb
71 .thumb_func
73 HAL_RNG_MspInit:
74 .LVL2:
75 .LFB135:
50:Src/rng.c ****
51:Src/rng.c **** void HAL_RNG_MspInit(RNG_HandleTypeDef* rngHandle)
52:Src/rng.c **** {
76 .loc 1 52 1 is_stmt 1 view -0
77 .cfi_startproc
78 @ args = 0, pretend = 0, frame = 8
79 @ frame_needed = 0, uses_anonymous_args = 0
80 @ link register save eliminated.
53:Src/rng.c ****
54:Src/rng.c **** if(rngHandle->Instance==RNG)
81 .loc 1 54 3 view .LVU10
82 .loc 1 54 15 is_stmt 0 view .LVU11
83 0000 0268 ldr r2, [r0]
84 .loc 1 54 5 view .LVU12
85 0002 094B ldr r3, .L14
86 0004 9A42 cmp r2, r3
87 0006 00D0 beq .L13
88 0008 7047 bx lr
89 .L13:
52:Src/rng.c ****
90 .loc 1 52 1 view .LVU13
91 000a 82B0 sub sp, sp, #8
92 .LCFI1:
93 .cfi_def_cfa_offset 8
55:Src/rng.c **** {
56:Src/rng.c **** /* USER CODE BEGIN RNG_MspInit 0 */
57:Src/rng.c ****
58:Src/rng.c **** /* USER CODE END RNG_MspInit 0 */
59:Src/rng.c **** /* RNG clock enable */
60:Src/rng.c **** __HAL_RCC_RNG_CLK_ENABLE();
94 .loc 1 60 5 is_stmt 1 view .LVU14
95 .LBB2:
96 .loc 1 60 5 view .LVU15
97 000c 0023 movs r3, #0
98 000e 0193 str r3, [sp, #4]
99 .loc 1 60 5 view .LVU16
100 0010 064B ldr r3, .L14+4
101 0012 5A6B ldr r2, [r3, #52]
102 0014 42F04002 orr r2, r2, #64
103 0018 5A63 str r2, [r3, #52]
104 .loc 1 60 5 view .LVU17
105 001a 5B6B ldr r3, [r3, #52]
106 001c 03F04003 and r3, r3, #64
107 0020 0193 str r3, [sp, #4]
108 .loc 1 60 5 view .LVU18
109 0022 019B ldr r3, [sp, #4]
110 .LBE2:
111 .loc 1 60 5 view .LVU19
61:Src/rng.c **** /* USER CODE BEGIN RNG_MspInit 1 */
ARM GAS /tmp/cc62HSfH.s page 4
62:Src/rng.c ****
63:Src/rng.c **** /* USER CODE END RNG_MspInit 1 */
64:Src/rng.c **** }
65:Src/rng.c **** }
112 .loc 1 65 1 is_stmt 0 view .LVU20
113 0024 02B0 add sp, sp, #8
114 .LCFI2:
115 .cfi_def_cfa_offset 0
116 @ sp needed
117 0026 7047 bx lr
118 .L15:
119 .align 2
120 .L14:
121 0028 00080650 .word 1342572544
122 002c 00380240 .word 1073887232
123 .cfi_endproc
124 .LFE135:
126 .section .text.HAL_RNG_MspDeInit,"ax",%progbits
127 .align 1
128 .global HAL_RNG_MspDeInit
129 .syntax unified
130 .thumb
131 .thumb_func
133 HAL_RNG_MspDeInit:
134 .LVL3:
135 .LFB136:
66:Src/rng.c ****
67:Src/rng.c **** void HAL_RNG_MspDeInit(RNG_HandleTypeDef* rngHandle)
68:Src/rng.c **** {
136 .loc 1 68 1 is_stmt 1 view -0
137 .cfi_startproc
138 @ args = 0, pretend = 0, frame = 0
139 @ frame_needed = 0, uses_anonymous_args = 0
140 @ link register save eliminated.
69:Src/rng.c ****
70:Src/rng.c **** if(rngHandle->Instance==RNG)
141 .loc 1 70 3 view .LVU22
142 .loc 1 70 15 is_stmt 0 view .LVU23
143 0000 0268 ldr r2, [r0]
144 .loc 1 70 5 view .LVU24
145 0002 054B ldr r3, .L19
146 0004 9A42 cmp r2, r3
147 0006 00D0 beq .L18
148 .L16:
71:Src/rng.c **** {
72:Src/rng.c **** /* USER CODE BEGIN RNG_MspDeInit 0 */
73:Src/rng.c ****
74:Src/rng.c **** /* USER CODE END RNG_MspDeInit 0 */
75:Src/rng.c **** /* Peripheral clock disable */
76:Src/rng.c **** __HAL_RCC_RNG_CLK_DISABLE();
77:Src/rng.c **** /* USER CODE BEGIN RNG_MspDeInit 1 */
78:Src/rng.c ****
79:Src/rng.c **** /* USER CODE END RNG_MspDeInit 1 */
80:Src/rng.c **** }
81:Src/rng.c **** }
149 .loc 1 81 1 view .LVU25
150 0008 7047 bx lr
ARM GAS /tmp/cc62HSfH.s page 5
151 .L18:
76:Src/rng.c **** /* USER CODE BEGIN RNG_MspDeInit 1 */
152 .loc 1 76 5 is_stmt 1 view .LVU26
153 000a 044A ldr r2, .L19+4
154 000c 536B ldr r3, [r2, #52]
155 000e 23F04003 bic r3, r3, #64
156 0012 5363 str r3, [r2, #52]
157 .loc 1 81 1 is_stmt 0 view .LVU27
158 0014 F8E7 b .L16
159 .L20:
160 0016 00BF .align 2
161 .L19:
162 0018 00080650 .word 1342572544
163 001c 00380240 .word 1073887232
164 .cfi_endproc
165 .LFE136:
167 .global hrng
168 .section .bss.hrng,"aw",%nobits
169 .align 2
170 .set .LANCHOR0,. + 0
173 hrng:
174 0000 00000000 .space 16
174 00000000
174 00000000
174 00000000
175 .text
176 .Letext0:
177 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
178 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
179 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
180 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
181 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h"
182 .file 7 "Inc/main.h"
183 .file 8 "Inc/rng.h"
ARM GAS /tmp/cc62HSfH.s page 6
DEFINED SYMBOLS
*ABS*:0000000000000000 rng.c
/tmp/cc62HSfH.s:20 .text.MX_RNG_Init:0000000000000000 $t
/tmp/cc62HSfH.s:26 .text.MX_RNG_Init:0000000000000000 MX_RNG_Init
/tmp/cc62HSfH.s:61 .text.MX_RNG_Init:0000000000000018 $d
/tmp/cc62HSfH.s:67 .text.HAL_RNG_MspInit:0000000000000000 $t
/tmp/cc62HSfH.s:73 .text.HAL_RNG_MspInit:0000000000000000 HAL_RNG_MspInit
/tmp/cc62HSfH.s:121 .text.HAL_RNG_MspInit:0000000000000028 $d
/tmp/cc62HSfH.s:127 .text.HAL_RNG_MspDeInit:0000000000000000 $t
/tmp/cc62HSfH.s:133 .text.HAL_RNG_MspDeInit:0000000000000000 HAL_RNG_MspDeInit
/tmp/cc62HSfH.s:162 .text.HAL_RNG_MspDeInit:0000000000000018 $d
/tmp/cc62HSfH.s:173 .bss.hrng:0000000000000000 hrng
/tmp/cc62HSfH.s:169 .bss.hrng:0000000000000000 $d
UNDEFINED SYMBOLS
HAL_RNG_Init
Error_Handler

583
build/rtc.lst Normal file
View File

@ -0,0 +1,583 @@
ARM GAS /tmp/ccF9G5yZ.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "rtc.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_RTC_Init,"ax",%progbits
20 .align 1
21 .global MX_RTC_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_RTC_Init:
27 .LFB134:
28 .file 1 "Src/rtc.c"
1:Src/rtc.c **** /* USER CODE BEGIN Header */
2:Src/rtc.c **** /**
3:Src/rtc.c **** ******************************************************************************
4:Src/rtc.c **** * @file rtc.c
5:Src/rtc.c **** * @brief This file provides code for the configuration
6:Src/rtc.c **** * of the RTC instances.
7:Src/rtc.c **** ******************************************************************************
8:Src/rtc.c **** * @attention
9:Src/rtc.c **** *
10:Src/rtc.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/rtc.c **** * All rights reserved.
12:Src/rtc.c **** *
13:Src/rtc.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/rtc.c **** * in the root directory of this software component.
15:Src/rtc.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/rtc.c **** *
17:Src/rtc.c **** ******************************************************************************
18:Src/rtc.c **** */
19:Src/rtc.c **** /* USER CODE END Header */
20:Src/rtc.c **** /* Includes ------------------------------------------------------------------*/
21:Src/rtc.c **** #include "rtc.h"
22:Src/rtc.c ****
23:Src/rtc.c **** /* USER CODE BEGIN 0 */
24:Src/rtc.c ****
25:Src/rtc.c **** /* USER CODE END 0 */
26:Src/rtc.c ****
27:Src/rtc.c **** RTC_HandleTypeDef hrtc;
28:Src/rtc.c ****
29:Src/rtc.c **** /* RTC init function */
30:Src/rtc.c **** void MX_RTC_Init(void)
ARM GAS /tmp/ccF9G5yZ.s page 2
31:Src/rtc.c **** {
29 .loc 1 31 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 64
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 10B5 push {r4, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 4, -8
37 .cfi_offset 14, -4
38 0002 90B0 sub sp, sp, #64
39 .LCFI1:
40 .cfi_def_cfa_offset 72
32:Src/rtc.c ****
33:Src/rtc.c **** /* USER CODE BEGIN RTC_Init 0 */
34:Src/rtc.c ****
35:Src/rtc.c **** /* USER CODE END RTC_Init 0 */
36:Src/rtc.c ****
37:Src/rtc.c **** RTC_TimeTypeDef sTime = {0};
41 .loc 1 37 3 view .LVU1
42 .loc 1 37 19 is_stmt 0 view .LVU2
43 0004 0024 movs r4, #0
44 0006 0B94 str r4, [sp, #44]
45 0008 0C94 str r4, [sp, #48]
46 000a 0D94 str r4, [sp, #52]
47 000c 0E94 str r4, [sp, #56]
48 000e 0F94 str r4, [sp, #60]
38:Src/rtc.c **** RTC_DateTypeDef sDate = {0};
49 .loc 1 38 3 is_stmt 1 view .LVU3
50 .loc 1 38 19 is_stmt 0 view .LVU4
51 0010 0A94 str r4, [sp, #40]
39:Src/rtc.c **** RTC_AlarmTypeDef sAlarm = {0};
52 .loc 1 39 3 is_stmt 1 view .LVU5
53 .loc 1 39 20 is_stmt 0 view .LVU6
54 0012 2822 movs r2, #40
55 0014 2146 mov r1, r4
56 0016 6846 mov r0, sp
57 0018 FFF7FEFF bl memset
58 .LVL0:
40:Src/rtc.c ****
41:Src/rtc.c **** /* USER CODE BEGIN RTC_Init 1 */
42:Src/rtc.c ****
43:Src/rtc.c **** /* USER CODE END RTC_Init 1 */
44:Src/rtc.c ****
45:Src/rtc.c **** /** Initialize RTC Only
46:Src/rtc.c **** */
47:Src/rtc.c **** hrtc.Instance = RTC;
59 .loc 1 47 3 is_stmt 1 view .LVU7
60 .loc 1 47 17 is_stmt 0 view .LVU8
61 001c 2948 ldr r0, .L11
62 001e 2A4B ldr r3, .L11+4
63 0020 0360 str r3, [r0]
48:Src/rtc.c **** hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
64 .loc 1 48 3 is_stmt 1 view .LVU9
65 .loc 1 48 24 is_stmt 0 view .LVU10
66 0022 4460 str r4, [r0, #4]
49:Src/rtc.c **** hrtc.Init.AsynchPrediv = 127;
ARM GAS /tmp/ccF9G5yZ.s page 3
67 .loc 1 49 3 is_stmt 1 view .LVU11
68 .loc 1 49 26 is_stmt 0 view .LVU12
69 0024 7F23 movs r3, #127
70 0026 8360 str r3, [r0, #8]
50:Src/rtc.c **** hrtc.Init.SynchPrediv = 255;
71 .loc 1 50 3 is_stmt 1 view .LVU13
72 .loc 1 50 25 is_stmt 0 view .LVU14
73 0028 FF23 movs r3, #255
74 002a C360 str r3, [r0, #12]
51:Src/rtc.c **** hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
75 .loc 1 51 3 is_stmt 1 view .LVU15
76 .loc 1 51 20 is_stmt 0 view .LVU16
77 002c 0461 str r4, [r0, #16]
52:Src/rtc.c **** hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
78 .loc 1 52 3 is_stmt 1 view .LVU17
79 .loc 1 52 28 is_stmt 0 view .LVU18
80 002e 4461 str r4, [r0, #20]
53:Src/rtc.c **** hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
81 .loc 1 53 3 is_stmt 1 view .LVU19
82 .loc 1 53 24 is_stmt 0 view .LVU20
83 0030 8461 str r4, [r0, #24]
54:Src/rtc.c **** if (HAL_RTC_Init(&hrtc) != HAL_OK)
84 .loc 1 54 3 is_stmt 1 view .LVU21
85 .loc 1 54 7 is_stmt 0 view .LVU22
86 0032 FFF7FEFF bl HAL_RTC_Init
87 .LVL1:
88 .loc 1 54 6 view .LVU23
89 0036 0028 cmp r0, #0
90 0038 37D1 bne .L7
91 .L2:
55:Src/rtc.c **** {
56:Src/rtc.c **** Error_Handler();
57:Src/rtc.c **** }
58:Src/rtc.c ****
59:Src/rtc.c **** /* USER CODE BEGIN Check_RTC_BKUP */
60:Src/rtc.c ****
61:Src/rtc.c **** /* USER CODE END Check_RTC_BKUP */
62:Src/rtc.c ****
63:Src/rtc.c **** /** Initialize RTC and set the Time and Date
64:Src/rtc.c **** */
65:Src/rtc.c **** sTime.Hours = 0x0;
92 .loc 1 65 3 is_stmt 1 view .LVU24
93 .loc 1 65 15 is_stmt 0 view .LVU25
94 003a 0023 movs r3, #0
95 003c 8DF82C30 strb r3, [sp, #44]
66:Src/rtc.c **** sTime.Minutes = 0x0;
96 .loc 1 66 3 is_stmt 1 view .LVU26
97 .loc 1 66 17 is_stmt 0 view .LVU27
98 0040 8DF82D30 strb r3, [sp, #45]
67:Src/rtc.c **** sTime.Seconds = 0x0;
99 .loc 1 67 3 is_stmt 1 view .LVU28
100 .loc 1 67 17 is_stmt 0 view .LVU29
101 0044 8DF82E30 strb r3, [sp, #46]
68:Src/rtc.c **** sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
102 .loc 1 68 3 is_stmt 1 view .LVU30
103 .loc 1 68 24 is_stmt 0 view .LVU31
104 0048 0E93 str r3, [sp, #56]
ARM GAS /tmp/ccF9G5yZ.s page 4
69:Src/rtc.c **** sTime.StoreOperation = RTC_STOREOPERATION_RESET;
105 .loc 1 69 3 is_stmt 1 view .LVU32
106 .loc 1 69 24 is_stmt 0 view .LVU33
107 004a 0F93 str r3, [sp, #60]
70:Src/rtc.c **** if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
108 .loc 1 70 3 is_stmt 1 view .LVU34
109 .loc 1 70 7 is_stmt 0 view .LVU35
110 004c 0122 movs r2, #1
111 004e 0BA9 add r1, sp, #44
112 0050 1C48 ldr r0, .L11
113 0052 FFF7FEFF bl HAL_RTC_SetTime
114 .LVL2:
115 .loc 1 70 6 view .LVU36
116 0056 58BB cbnz r0, .L8
117 .L3:
71:Src/rtc.c **** {
72:Src/rtc.c **** Error_Handler();
73:Src/rtc.c **** }
74:Src/rtc.c **** sDate.WeekDay = RTC_WEEKDAY_MONDAY;
118 .loc 1 74 3 is_stmt 1 view .LVU37
119 .loc 1 74 17 is_stmt 0 view .LVU38
120 0058 0122 movs r2, #1
121 005a 8DF82820 strb r2, [sp, #40]
75:Src/rtc.c **** sDate.Month = RTC_MONTH_JANUARY;
122 .loc 1 75 3 is_stmt 1 view .LVU39
123 .loc 1 75 15 is_stmt 0 view .LVU40
124 005e 8DF82920 strb r2, [sp, #41]
76:Src/rtc.c **** sDate.Date = 0x1;
125 .loc 1 76 3 is_stmt 1 view .LVU41
126 .loc 1 76 14 is_stmt 0 view .LVU42
127 0062 8DF82A20 strb r2, [sp, #42]
77:Src/rtc.c **** sDate.Year = 0x0;
128 .loc 1 77 3 is_stmt 1 view .LVU43
129 .loc 1 77 14 is_stmt 0 view .LVU44
130 0066 0023 movs r3, #0
131 0068 8DF82B30 strb r3, [sp, #43]
78:Src/rtc.c ****
79:Src/rtc.c **** if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
132 .loc 1 79 3 is_stmt 1 view .LVU45
133 .loc 1 79 7 is_stmt 0 view .LVU46
134 006c 0AA9 add r1, sp, #40
135 006e 1548 ldr r0, .L11
136 0070 FFF7FEFF bl HAL_RTC_SetDate
137 .LVL3:
138 .loc 1 79 6 view .LVU47
139 0074 F8B9 cbnz r0, .L9
140 .L4:
80:Src/rtc.c **** {
81:Src/rtc.c **** Error_Handler();
82:Src/rtc.c **** }
83:Src/rtc.c ****
84:Src/rtc.c **** /** Enable the Alarm A
85:Src/rtc.c **** */
86:Src/rtc.c **** sAlarm.AlarmTime.Hours = 0x0;
141 .loc 1 86 3 is_stmt 1 view .LVU48
142 .loc 1 86 26 is_stmt 0 view .LVU49
143 0076 0023 movs r3, #0
ARM GAS /tmp/ccF9G5yZ.s page 5
144 0078 8DF80030 strb r3, [sp]
87:Src/rtc.c **** sAlarm.AlarmTime.Minutes = 0x0;
145 .loc 1 87 3 is_stmt 1 view .LVU50
146 .loc 1 87 28 is_stmt 0 view .LVU51
147 007c 8DF80130 strb r3, [sp, #1]
88:Src/rtc.c **** sAlarm.AlarmTime.Seconds = 0x0;
148 .loc 1 88 3 is_stmt 1 view .LVU52
149 .loc 1 88 28 is_stmt 0 view .LVU53
150 0080 8DF80230 strb r3, [sp, #2]
89:Src/rtc.c **** sAlarm.AlarmTime.SubSeconds = 0x0;
151 .loc 1 89 3 is_stmt 1 view .LVU54
152 .loc 1 89 31 is_stmt 0 view .LVU55
153 0084 0193 str r3, [sp, #4]
90:Src/rtc.c **** sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
154 .loc 1 90 3 is_stmt 1 view .LVU56
155 .loc 1 90 35 is_stmt 0 view .LVU57
156 0086 0393 str r3, [sp, #12]
91:Src/rtc.c **** sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET;
157 .loc 1 91 3 is_stmt 1 view .LVU58
158 .loc 1 91 35 is_stmt 0 view .LVU59
159 0088 0493 str r3, [sp, #16]
92:Src/rtc.c **** sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
160 .loc 1 92 3 is_stmt 1 view .LVU60
161 .loc 1 92 20 is_stmt 0 view .LVU61
162 008a 0593 str r3, [sp, #20]
93:Src/rtc.c **** sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL;
163 .loc 1 93 3 is_stmt 1 view .LVU62
164 .loc 1 93 29 is_stmt 0 view .LVU63
165 008c 0693 str r3, [sp, #24]
94:Src/rtc.c **** sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE;
166 .loc 1 94 3 is_stmt 1 view .LVU64
167 .loc 1 94 30 is_stmt 0 view .LVU65
168 008e 0793 str r3, [sp, #28]
95:Src/rtc.c **** sAlarm.AlarmDateWeekDay = 0x1;
169 .loc 1 95 3 is_stmt 1 view .LVU66
170 .loc 1 95 27 is_stmt 0 view .LVU67
171 0090 0122 movs r2, #1
172 0092 8DF82020 strb r2, [sp, #32]
96:Src/rtc.c **** sAlarm.Alarm = RTC_ALARM_A;
173 .loc 1 96 3 is_stmt 1 view .LVU68
174 .loc 1 96 16 is_stmt 0 view .LVU69
175 0096 4FF48073 mov r3, #256
176 009a 0993 str r3, [sp, #36]
97:Src/rtc.c **** if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
177 .loc 1 97 3 is_stmt 1 view .LVU70
178 .loc 1 97 7 is_stmt 0 view .LVU71
179 009c 6946 mov r1, sp
180 009e 0948 ldr r0, .L11
181 00a0 FFF7FEFF bl HAL_RTC_SetAlarm
182 .LVL4:
183 .loc 1 97 6 view .LVU72
184 00a4 50B9 cbnz r0, .L10
185 .L1:
98:Src/rtc.c **** {
99:Src/rtc.c **** Error_Handler();
100:Src/rtc.c **** }
101:Src/rtc.c **** /* USER CODE BEGIN RTC_Init 2 */
ARM GAS /tmp/ccF9G5yZ.s page 6
102:Src/rtc.c ****
103:Src/rtc.c **** /* USER CODE END RTC_Init 2 */
104:Src/rtc.c ****
105:Src/rtc.c **** }
186 .loc 1 105 1 view .LVU73
187 00a6 10B0 add sp, sp, #64
188 .LCFI2:
189 .cfi_remember_state
190 .cfi_def_cfa_offset 8
191 @ sp needed
192 00a8 10BD pop {r4, pc}
193 .L7:
194 .LCFI3:
195 .cfi_restore_state
56:Src/rtc.c **** }
196 .loc 1 56 5 is_stmt 1 view .LVU74
197 00aa FFF7FEFF bl Error_Handler
198 .LVL5:
199 00ae C4E7 b .L2
200 .L8:
72:Src/rtc.c **** }
201 .loc 1 72 5 view .LVU75
202 00b0 FFF7FEFF bl Error_Handler
203 .LVL6:
204 00b4 D0E7 b .L3
205 .L9:
81:Src/rtc.c **** }
206 .loc 1 81 5 view .LVU76
207 00b6 FFF7FEFF bl Error_Handler
208 .LVL7:
209 00ba DCE7 b .L4
210 .L10:
99:Src/rtc.c **** }
211 .loc 1 99 5 view .LVU77
212 00bc FFF7FEFF bl Error_Handler
213 .LVL8:
214 .loc 1 105 1 is_stmt 0 view .LVU78
215 00c0 F1E7 b .L1
216 .L12:
217 00c2 00BF .align 2
218 .L11:
219 00c4 00000000 .word .LANCHOR0
220 00c8 00280040 .word 1073752064
221 .cfi_endproc
222 .LFE134:
224 .section .text.HAL_RTC_MspInit,"ax",%progbits
225 .align 1
226 .global HAL_RTC_MspInit
227 .syntax unified
228 .thumb
229 .thumb_func
231 HAL_RTC_MspInit:
232 .LVL9:
233 .LFB135:
106:Src/rtc.c ****
107:Src/rtc.c **** void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
108:Src/rtc.c **** {
ARM GAS /tmp/ccF9G5yZ.s page 7
234 .loc 1 108 1 is_stmt 1 view -0
235 .cfi_startproc
236 @ args = 0, pretend = 0, frame = 16
237 @ frame_needed = 0, uses_anonymous_args = 0
238 .loc 1 108 1 is_stmt 0 view .LVU80
239 0000 00B5 push {lr}
240 .LCFI4:
241 .cfi_def_cfa_offset 4
242 .cfi_offset 14, -4
243 0002 85B0 sub sp, sp, #20
244 .LCFI5:
245 .cfi_def_cfa_offset 24
109:Src/rtc.c ****
110:Src/rtc.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
246 .loc 1 110 3 is_stmt 1 view .LVU81
247 .loc 1 110 28 is_stmt 0 view .LVU82
248 0004 0023 movs r3, #0
249 0006 0093 str r3, [sp]
250 0008 0193 str r3, [sp, #4]
251 000a 0293 str r3, [sp, #8]
252 000c 0393 str r3, [sp, #12]
111:Src/rtc.c **** if(rtcHandle->Instance==RTC)
253 .loc 1 111 3 is_stmt 1 view .LVU83
254 .loc 1 111 15 is_stmt 0 view .LVU84
255 000e 0268 ldr r2, [r0]
256 .loc 1 111 5 view .LVU85
257 0010 0B4B ldr r3, .L19
258 0012 9A42 cmp r2, r3
259 0014 02D0 beq .L17
260 .LVL10:
261 .L13:
112:Src/rtc.c **** {
113:Src/rtc.c **** /* USER CODE BEGIN RTC_MspInit 0 */
114:Src/rtc.c ****
115:Src/rtc.c **** /* USER CODE END RTC_MspInit 0 */
116:Src/rtc.c ****
117:Src/rtc.c **** /** Initializes the peripherals clock
118:Src/rtc.c **** */
119:Src/rtc.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
120:Src/rtc.c **** PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
121:Src/rtc.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
122:Src/rtc.c **** {
123:Src/rtc.c **** Error_Handler();
124:Src/rtc.c **** }
125:Src/rtc.c ****
126:Src/rtc.c **** /* RTC clock enable */
127:Src/rtc.c **** __HAL_RCC_RTC_ENABLE();
128:Src/rtc.c **** /* USER CODE BEGIN RTC_MspInit 1 */
129:Src/rtc.c ****
130:Src/rtc.c **** /* USER CODE END RTC_MspInit 1 */
131:Src/rtc.c **** }
132:Src/rtc.c **** }
262 .loc 1 132 1 view .LVU86
263 0016 05B0 add sp, sp, #20
264 .LCFI6:
265 .cfi_remember_state
266 .cfi_def_cfa_offset 4
ARM GAS /tmp/ccF9G5yZ.s page 8
267 @ sp needed
268 0018 5DF804FB ldr pc, [sp], #4
269 .LVL11:
270 .L17:
271 .LCFI7:
272 .cfi_restore_state
119:Src/rtc.c **** PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
273 .loc 1 119 5 is_stmt 1 view .LVU87
119:Src/rtc.c **** PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
274 .loc 1 119 46 is_stmt 0 view .LVU88
275 001c 0223 movs r3, #2
276 001e 0093 str r3, [sp]
120:Src/rtc.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
277 .loc 1 120 5 is_stmt 1 view .LVU89
120:Src/rtc.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
278 .loc 1 120 43 is_stmt 0 view .LVU90
279 0020 4FF48073 mov r3, #256
280 0024 0393 str r3, [sp, #12]
121:Src/rtc.c **** {
281 .loc 1 121 5 is_stmt 1 view .LVU91
121:Src/rtc.c **** {
282 .loc 1 121 9 is_stmt 0 view .LVU92
283 0026 6846 mov r0, sp
284 .LVL12:
121:Src/rtc.c **** {
285 .loc 1 121 9 view .LVU93
286 0028 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig
287 .LVL13:
121:Src/rtc.c **** {
288 .loc 1 121 8 view .LVU94
289 002c 20B9 cbnz r0, .L18
290 .L15:
127:Src/rtc.c **** /* USER CODE BEGIN RTC_MspInit 1 */
291 .loc 1 127 5 is_stmt 1 view .LVU95
292 002e 054B ldr r3, .L19+4
293 0030 0122 movs r2, #1
294 0032 C3F83C2E str r2, [r3, #3644]
295 .loc 1 132 1 is_stmt 0 view .LVU96
296 0036 EEE7 b .L13
297 .L18:
123:Src/rtc.c **** }
298 .loc 1 123 7 is_stmt 1 view .LVU97
299 0038 FFF7FEFF bl Error_Handler
300 .LVL14:
301 003c F7E7 b .L15
302 .L20:
303 003e 00BF .align 2
304 .L19:
305 0040 00280040 .word 1073752064
306 0044 00004742 .word 1111949312
307 .cfi_endproc
308 .LFE135:
310 .section .text.HAL_RTC_MspDeInit,"ax",%progbits
311 .align 1
312 .global HAL_RTC_MspDeInit
313 .syntax unified
314 .thumb
ARM GAS /tmp/ccF9G5yZ.s page 9
315 .thumb_func
317 HAL_RTC_MspDeInit:
318 .LVL15:
319 .LFB136:
133:Src/rtc.c ****
134:Src/rtc.c **** void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
135:Src/rtc.c **** {
320 .loc 1 135 1 view -0
321 .cfi_startproc
322 @ args = 0, pretend = 0, frame = 0
323 @ frame_needed = 0, uses_anonymous_args = 0
324 @ link register save eliminated.
136:Src/rtc.c ****
137:Src/rtc.c **** if(rtcHandle->Instance==RTC)
325 .loc 1 137 3 view .LVU99
326 .loc 1 137 15 is_stmt 0 view .LVU100
327 0000 0268 ldr r2, [r0]
328 .loc 1 137 5 view .LVU101
329 0002 044B ldr r3, .L24
330 0004 9A42 cmp r2, r3
331 0006 00D0 beq .L23
332 .L21:
138:Src/rtc.c **** {
139:Src/rtc.c **** /* USER CODE BEGIN RTC_MspDeInit 0 */
140:Src/rtc.c ****
141:Src/rtc.c **** /* USER CODE END RTC_MspDeInit 0 */
142:Src/rtc.c **** /* Peripheral clock disable */
143:Src/rtc.c **** __HAL_RCC_RTC_DISABLE();
144:Src/rtc.c **** /* USER CODE BEGIN RTC_MspDeInit 1 */
145:Src/rtc.c ****
146:Src/rtc.c **** /* USER CODE END RTC_MspDeInit 1 */
147:Src/rtc.c **** }
148:Src/rtc.c **** }
333 .loc 1 148 1 view .LVU102
334 0008 7047 bx lr
335 .L23:
143:Src/rtc.c **** /* USER CODE BEGIN RTC_MspDeInit 1 */
336 .loc 1 143 5 is_stmt 1 view .LVU103
337 000a 034B ldr r3, .L24+4
338 000c 0022 movs r2, #0
339 000e C3F83C2E str r2, [r3, #3644]
340 .loc 1 148 1 is_stmt 0 view .LVU104
341 0012 F9E7 b .L21
342 .L25:
343 .align 2
344 .L24:
345 0014 00280040 .word 1073752064
346 0018 00004742 .word 1111949312
347 .cfi_endproc
348 .LFE136:
350 .global hrtc
351 .section .bss.hrtc,"aw",%nobits
352 .align 2
353 .set .LANCHOR0,. + 0
356 hrtc:
357 0000 00000000 .space 32
357 00000000
ARM GAS /tmp/ccF9G5yZ.s page 10
357 00000000
357 00000000
357 00000000
358 .text
359 .Letext0:
360 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
361 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
362 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
363 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
364 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
365 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h"
366 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h"
367 .file 9 "Inc/main.h"
368 .file 10 "Inc/rtc.h"
369 .file 11 "<built-in>"
ARM GAS /tmp/ccF9G5yZ.s page 11
DEFINED SYMBOLS
*ABS*:0000000000000000 rtc.c
/tmp/ccF9G5yZ.s:20 .text.MX_RTC_Init:0000000000000000 $t
/tmp/ccF9G5yZ.s:26 .text.MX_RTC_Init:0000000000000000 MX_RTC_Init
/tmp/ccF9G5yZ.s:219 .text.MX_RTC_Init:00000000000000c4 $d
/tmp/ccF9G5yZ.s:225 .text.HAL_RTC_MspInit:0000000000000000 $t
/tmp/ccF9G5yZ.s:231 .text.HAL_RTC_MspInit:0000000000000000 HAL_RTC_MspInit
/tmp/ccF9G5yZ.s:305 .text.HAL_RTC_MspInit:0000000000000040 $d
/tmp/ccF9G5yZ.s:311 .text.HAL_RTC_MspDeInit:0000000000000000 $t
/tmp/ccF9G5yZ.s:317 .text.HAL_RTC_MspDeInit:0000000000000000 HAL_RTC_MspDeInit
/tmp/ccF9G5yZ.s:345 .text.HAL_RTC_MspDeInit:0000000000000014 $d
/tmp/ccF9G5yZ.s:356 .bss.hrtc:0000000000000000 hrtc
/tmp/ccF9G5yZ.s:352 .bss.hrtc:0000000000000000 $d
UNDEFINED SYMBOLS
memset
HAL_RTC_Init
HAL_RTC_SetTime
HAL_RTC_SetDate
HAL_RTC_SetAlarm
Error_Handler
HAL_RCCEx_PeriphCLKConfig

1684
build/stm32f4xx_hal.lst Normal file
View File

File diff suppressed because it is too large Load Diff

4555
build/stm32f4xx_hal_cortex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

4593
build/stm32f4xx_hal_dma.lst Normal file
View File

File diff suppressed because it is too large Load Diff

3343
build/stm32f4xx_hal_dma_ex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

1567
build/stm32f4xx_hal_exti.lst Normal file
View File

File diff suppressed because it is too large Load Diff

2576
build/stm32f4xx_hal_flash.lst Normal file
View File

File diff suppressed because it is too large Load Diff

2838
build/stm32f4xx_hal_flash_ex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

29
build/stm32f4xx_hal_flash_ramfunc.lst Normal file
View File

@ -0,0 +1,29 @@
ARM GAS /tmp/cc9Sz8Ii.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_flash_ramfunc.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .Letext0:
ARM GAS /tmp/cc9Sz8Ii.s page 2
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_hal_flash_ramfunc.c
NO UNDEFINED SYMBOLS

1758
build/stm32f4xx_hal_gpio.lst Normal file
View File

File diff suppressed because it is too large Load Diff

450
build/stm32f4xx_hal_iwdg.lst Normal file
View File

@ -0,0 +1,450 @@
ARM GAS /tmp/ccFWyvBN.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_iwdg.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.HAL_IWDG_Init,"ax",%progbits
20 .align 1
21 .global HAL_IWDG_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 HAL_IWDG_Init:
27 .LVL0:
28 .LFB134:
29 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c"
1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /**
2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ******************************************************************************
3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @file stm32f4xx_hal_iwdg.c
4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @author MCD Application Team
5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief IWDG HAL module driver.
6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * functionalities of the Independent Watchdog (IWDG) peripheral:
8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * + Initialization and Start functions
9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * + IO operation functions
10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ******************************************************************************
12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @attention
13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * Copyright (c) 2016 STMicroelectronics.
15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * All rights reserved.
16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * in the root directory of this software component.
19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ******************************************************************************
22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @verbatim
23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ==============================================================================
24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ##### IWDG Generic features #####
25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ==============================================================================
26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..]
27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) The IWDG can be started by either software or hardware (configurable
28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** through option byte).
29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
ARM GAS /tmp/ccFWyvBN.s page 2
30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** active even if the main clock fails.
32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Once the IWDG is started, the LSI is forced ON and both cannot be
34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** disabled. The counter starts counting down from the reset value (0xFFF).
35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** When it reaches the end of count value (0x000) a reset signal is
36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** generated (IWDG reset).
37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** the IWDG_RLR value is reloaded into the counter and the watchdog reset
40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** is prevented.
41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) The IWDG is implemented in the VDD voltage domain that is still functional
43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** reset occurs.
46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Debug mode: When the microcontroller enters debug mode (core halted),
48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** the IWDG counter either continues to work normally or stops, depending
49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** on DBG_IWDG_STOP configuration bit in DBG module, accessible through
50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** The IWDG timeout may vary due to LSI clock frequency dispersion.
54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** STM32F4xx devices provide the capability to measure the LSI clock
55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** frequency (LSI clock is internally connected to TIM5 CH4 input capture).
56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** The measured value can be used to have an IWDG timeout with an
57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** acceptable accuracy.
58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..] Default timeout value (necessary for IWDG_SR status register update):
60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** This frequency being subject to variations as mentioned above, the
62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** below) may become too short or too long.
64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** In such cases, this default timeout value can be tuned by redefining
65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** the constant LSI_VALUE at user-application level (based, for instance,
66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** on the measured LSI clock frequency as explained above).
67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ##### How to use this driver #####
69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ==============================================================================
70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..]
71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (#) Use IWDG using HAL_IWDG_Init() function to :
72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** clock is forced ON and IWDG counter starts counting down.
74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (++) Enable write access to configuration registers:
75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** IWDG_PR and IWDG_RLR.
76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (++) Configure the IWDG prescaler and counter reload value. This reload
77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** value will be loaded in the IWDG counter each time the watchdog is
78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** reloaded, then the IWDG will start counting down from this value.
79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (++) Wait for status flags to be reset.
80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (#) Then the application program must refresh the IWDG counter at regular
82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** intervals during normal operation to prevent an MCU reset, using
83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** HAL_IWDG_Refresh() function.
84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *** IWDG HAL driver macros list ***
86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ====================================
ARM GAS /tmp/ccFWyvBN.s page 3
87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..]
88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** Below the list of most used macros in IWDG HAL driver:
89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) __HAL_IWDG_START: Enable the IWDG peripheral
90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** the reload register
92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @endverbatim
94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Includes ------------------------------------------------------------------*/
97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** #include "stm32f4xx_hal.h"
98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @addtogroup STM32F4xx_HAL_Driver
100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** #ifdef HAL_IWDG_MODULE_ENABLED
104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @addtogroup IWDG
105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief IWDG HAL module driver.
106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Private typedef -----------------------------------------------------------*/
110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Private define ------------------------------------------------------------*/
111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @defgroup IWDG_Private_Defines IWDG Private Defines
112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Status register needs up to 5 LSI clock periods divided by the clock
115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** prescaler to be updated. The number of LSI clock periods is upper-rounded to
116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** 6 for the timeout value calculation.
117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** The timeout value is calculated using the highest prescaler (256) and
118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** the LSI_VALUE constant. The value of this constant can be changed by the user
119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** to take into account possible LSI clock period variations.
120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** The timeout value is multiplied by 1000 to be converted in milliseconds.
121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** LSI startup time is also considered here by adding LSI_STARTUP_TIME
122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** converted in milliseconds. */
123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** #define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ((LSI_STARTUP_TIME / 1000UL) + 1UL))
125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /**
127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @}
128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Private macro -------------------------------------------------------------*/
131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Private variables ---------------------------------------------------------*/
132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Private function prototypes -----------------------------------------------*/
133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Exported functions --------------------------------------------------------*/
134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions
136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions_Group1
140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief Initialization and Start functions.
141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @verbatim
143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ===============================================================================
ARM GAS /tmp/ccFWyvBN.s page 4
144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ##### Initialization and Start functions #####
145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ===============================================================================
146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..] This section provides functions allowing to:
147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Initialize the IWDG according to the specified parameters in the
148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** IWDG_InitTypeDef of associated handle.
149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** is reloaded in order to exit function with correct time base.
151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @endverbatim
153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /**
157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief Initialize the IWDG according to the specified parameters in the
158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * IWDG_InitTypeDef and start watchdog. Before exiting function,
159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * watchdog is refreshed in order to have correct time base.
160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * the configuration information for the specified IWDG module.
162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @retval HAL status
163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
30 .loc 1 165 1 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** uint32_t tickstart;
34 .loc 1 166 3 view .LVU1
167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Check the IWDG handle allocation */
169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** if (hiwdg == NULL)
35 .loc 1 169 3 view .LVU2
36 .loc 1 169 6 is_stmt 0 view .LVU3
37 0000 50B3 cbz r0, .L5
165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** uint32_t tickstart;
38 .loc 1 165 1 view .LVU4
39 0002 38B5 push {r3, r4, r5, lr}
40 .LCFI0:
41 .cfi_def_cfa_offset 16
42 .cfi_offset 3, -16
43 .cfi_offset 4, -12
44 .cfi_offset 5, -8
45 .cfi_offset 14, -4
46 0004 0446 mov r4, r0
170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** return HAL_ERROR;
172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Check the parameters */
175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
47 .loc 1 175 3 is_stmt 1 view .LVU5
176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
48 .loc 1 176 3 view .LVU6
177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
49 .loc 1 177 3 view .LVU7
178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Enable IWDG. LSI is turned on automatically */
ARM GAS /tmp/ccFWyvBN.s page 5
180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** __HAL_IWDG_START(hiwdg);
50 .loc 1 180 3 view .LVU8
51 0006 0368 ldr r3, [r0]
52 0008 4CF6CC42 movw r2, #52428
53 000c 1A60 str r2, [r3]
181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Enable write access to IWDG_PR and IWDG_RLR registers by writing
183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** 0x5555 in KR */
184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** IWDG_ENABLE_WRITE_ACCESS(hiwdg);
54 .loc 1 184 3 view .LVU9
55 000e 0368 ldr r3, [r0]
56 0010 45F25552 movw r2, #21845
57 0014 1A60 str r2, [r3]
185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Write to IWDG registers the Prescaler & Reload values to work with */
187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** hiwdg->Instance->PR = hiwdg->Init.Prescaler;
58 .loc 1 187 3 view .LVU10
59 .loc 1 187 8 is_stmt 0 view .LVU11
60 0016 0368 ldr r3, [r0]
61 .loc 1 187 36 view .LVU12
62 0018 4268 ldr r2, [r0, #4]
63 .loc 1 187 23 view .LVU13
64 001a 5A60 str r2, [r3, #4]
188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** hiwdg->Instance->RLR = hiwdg->Init.Reload;
65 .loc 1 188 3 is_stmt 1 view .LVU14
66 .loc 1 188 8 is_stmt 0 view .LVU15
67 001c 0368 ldr r3, [r0]
68 .loc 1 188 37 view .LVU16
69 001e 8268 ldr r2, [r0, #8]
70 .loc 1 188 24 view .LVU17
71 0020 9A60 str r2, [r3, #8]
189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Check pending flag, if previous update not done, return timeout */
191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** tickstart = HAL_GetTick();
72 .loc 1 191 3 is_stmt 1 view .LVU18
73 .loc 1 191 15 is_stmt 0 view .LVU19
74 0022 FFF7FEFF bl HAL_GetTick
75 .LVL1:
76 .loc 1 191 15 view .LVU20
77 0026 0546 mov r5, r0
78 .LVL2:
192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Wait for register to be updated */
194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
79 .loc 1 194 3 is_stmt 1 view .LVU21
80 .L3:
81 .loc 1 194 9 view .LVU22
82 .loc 1 194 16 is_stmt 0 view .LVU23
83 0028 2368 ldr r3, [r4]
84 .loc 1 194 26 view .LVU24
85 002a DA68 ldr r2, [r3, #12]
86 .loc 1 194 9 view .LVU25
87 002c 12F0030F tst r2, #3
88 0030 0DD0 beq .L11
195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
89 .loc 1 196 5 is_stmt 1 view .LVU26
ARM GAS /tmp/ccFWyvBN.s page 6
90 .loc 1 196 10 is_stmt 0 view .LVU27
91 0032 FFF7FEFF bl HAL_GetTick
92 .LVL3:
93 .loc 1 196 24 view .LVU28
94 0036 401B subs r0, r0, r5
95 .loc 1 196 8 view .LVU29
96 0038 41F60103 movw r3, #6145
97 003c 9842 cmp r0, r3
98 003e F3D9 bls .L3
197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
99 .loc 1 198 7 is_stmt 1 view .LVU30
100 .loc 1 198 17 is_stmt 0 view .LVU31
101 0040 2368 ldr r3, [r4]
102 .loc 1 198 27 view .LVU32
103 0042 DB68 ldr r3, [r3, #12]
104 .loc 1 198 10 view .LVU33
105 0044 13F0030F tst r3, #3
106 0048 EED0 beq .L3
199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** return HAL_TIMEOUT;
107 .loc 1 200 16 view .LVU34
108 004a 0320 movs r0, #3
109 004c 03E0 b .L2
110 .L11:
201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Reload IWDG counter with value defined in the reload register */
206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** __HAL_IWDG_RELOAD_COUNTER(hiwdg);
111 .loc 1 206 3 is_stmt 1 view .LVU35
112 004e 4AF6AA22 movw r2, #43690
113 0052 1A60 str r2, [r3]
207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Return function status */
209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** return HAL_OK;
114 .loc 1 209 3 view .LVU36
115 .loc 1 209 10 is_stmt 0 view .LVU37
116 0054 0020 movs r0, #0
117 .L2:
210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
118 .loc 1 210 1 view .LVU38
119 0056 38BD pop {r3, r4, r5, pc}
120 .LVL4:
121 .L5:
122 .LCFI1:
123 .cfi_def_cfa_offset 0
124 .cfi_restore 3
125 .cfi_restore 4
126 .cfi_restore 5
127 .cfi_restore 14
171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
128 .loc 1 171 12 view .LVU39
129 0058 0120 movs r0, #1
130 .LVL5:
131 .loc 1 210 1 view .LVU40
ARM GAS /tmp/ccFWyvBN.s page 7
132 005a 7047 bx lr
133 .cfi_endproc
134 .LFE134:
136 .section .text.HAL_IWDG_Refresh,"ax",%progbits
137 .align 1
138 .global HAL_IWDG_Refresh
139 .syntax unified
140 .thumb
141 .thumb_func
143 HAL_IWDG_Refresh:
144 .LVL6:
145 .LFB135:
211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /**
214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @}
215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions_Group2
219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief IO operation functions
220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** *
221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @verbatim
222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ===============================================================================
223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ##### IO operation functions #####
224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** ===============================================================================
225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** [..] This section provides functions allowing to:
226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** (+) Refresh the IWDG.
227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** @endverbatim
229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @{
230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /**
233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @brief Refresh the IWDG.
234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * the configuration information for the specified IWDG module.
236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** * @retval HAL status
237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** */
238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** {
146 .loc 1 239 1 is_stmt 1 view -0
147 .cfi_startproc
148 @ args = 0, pretend = 0, frame = 0
149 @ frame_needed = 0, uses_anonymous_args = 0
150 @ link register save eliminated.
240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Reload IWDG counter with value defined in the reload register */
241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** __HAL_IWDG_RELOAD_COUNTER(hiwdg);
151 .loc 1 241 3 view .LVU42
152 0000 0368 ldr r3, [r0]
153 0002 4AF6AA22 movw r2, #43690
154 0006 1A60 str r2, [r3]
242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c ****
243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** /* Return function status */
244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** return HAL_OK;
155 .loc 1 244 3 view .LVU43
245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c **** }
ARM GAS /tmp/ccFWyvBN.s page 8
156 .loc 1 245 1 is_stmt 0 view .LVU44
157 0008 0020 movs r0, #0
158 .LVL7:
159 .loc 1 245 1 view .LVU45
160 000a 7047 bx lr
161 .cfi_endproc
162 .LFE135:
164 .text
165 .Letext0:
166 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
167 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
168 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
169 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
170 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h"
171 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/ccFWyvBN.s page 9
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_hal_iwdg.c
/tmp/ccFWyvBN.s:20 .text.HAL_IWDG_Init:0000000000000000 $t
/tmp/ccFWyvBN.s:26 .text.HAL_IWDG_Init:0000000000000000 HAL_IWDG_Init
/tmp/ccFWyvBN.s:137 .text.HAL_IWDG_Refresh:0000000000000000 $t
/tmp/ccFWyvBN.s:143 .text.HAL_IWDG_Refresh:0000000000000000 HAL_IWDG_Refresh
UNDEFINED SYMBOLS
HAL_GetTick

183
build/stm32f4xx_hal_msp.lst Normal file
View File

@ -0,0 +1,183 @@
ARM GAS /tmp/ccI17HJx.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_msp.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.HAL_MspInit,"ax",%progbits
20 .align 1
21 .global HAL_MspInit
22 .syntax unified
23 .thumb
24 .thumb_func
26 HAL_MspInit:
27 .LFB134:
28 .file 1 "Src/stm32f4xx_hal_msp.c"
1:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Src/stm32f4xx_hal_msp.c **** /**
3:Src/stm32f4xx_hal_msp.c **** ******************************************************************************
4:Src/stm32f4xx_hal_msp.c **** * @file stm32f4xx_hal_msp.c
5:Src/stm32f4xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
6:Src/stm32f4xx_hal_msp.c **** * and de-Initialization codes.
7:Src/stm32f4xx_hal_msp.c **** ******************************************************************************
8:Src/stm32f4xx_hal_msp.c **** * @attention
9:Src/stm32f4xx_hal_msp.c **** *
10:Src/stm32f4xx_hal_msp.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/stm32f4xx_hal_msp.c **** * All rights reserved.
12:Src/stm32f4xx_hal_msp.c **** *
13:Src/stm32f4xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/stm32f4xx_hal_msp.c **** * in the root directory of this software component.
15:Src/stm32f4xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/stm32f4xx_hal_msp.c **** *
17:Src/stm32f4xx_hal_msp.c **** ******************************************************************************
18:Src/stm32f4xx_hal_msp.c **** */
19:Src/stm32f4xx_hal_msp.c **** /* USER CODE END Header */
20:Src/stm32f4xx_hal_msp.c ****
21:Src/stm32f4xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
22:Src/stm32f4xx_hal_msp.c **** #include "main.h"
23:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Includes */
24:Src/stm32f4xx_hal_msp.c ****
25:Src/stm32f4xx_hal_msp.c **** /* USER CODE END Includes */
26:Src/stm32f4xx_hal_msp.c ****
27:Src/stm32f4xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
28:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN TD */
29:Src/stm32f4xx_hal_msp.c ****
30:Src/stm32f4xx_hal_msp.c **** /* USER CODE END TD */
ARM GAS /tmp/ccI17HJx.s page 2
31:Src/stm32f4xx_hal_msp.c ****
32:Src/stm32f4xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
33:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Define */
34:Src/stm32f4xx_hal_msp.c ****
35:Src/stm32f4xx_hal_msp.c **** /* USER CODE END Define */
36:Src/stm32f4xx_hal_msp.c ****
37:Src/stm32f4xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
38:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Macro */
39:Src/stm32f4xx_hal_msp.c ****
40:Src/stm32f4xx_hal_msp.c **** /* USER CODE END Macro */
41:Src/stm32f4xx_hal_msp.c ****
42:Src/stm32f4xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
43:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PV */
44:Src/stm32f4xx_hal_msp.c ****
45:Src/stm32f4xx_hal_msp.c **** /* USER CODE END PV */
46:Src/stm32f4xx_hal_msp.c ****
47:Src/stm32f4xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
48:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PFP */
49:Src/stm32f4xx_hal_msp.c ****
50:Src/stm32f4xx_hal_msp.c **** /* USER CODE END PFP */
51:Src/stm32f4xx_hal_msp.c ****
52:Src/stm32f4xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
53:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
54:Src/stm32f4xx_hal_msp.c ****
55:Src/stm32f4xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
56:Src/stm32f4xx_hal_msp.c ****
57:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN 0 */
58:Src/stm32f4xx_hal_msp.c ****
59:Src/stm32f4xx_hal_msp.c **** /* USER CODE END 0 */
60:Src/stm32f4xx_hal_msp.c **** /**
61:Src/stm32f4xx_hal_msp.c **** * Initializes the Global MSP.
62:Src/stm32f4xx_hal_msp.c **** */
63:Src/stm32f4xx_hal_msp.c **** void HAL_MspInit(void)
64:Src/stm32f4xx_hal_msp.c **** {
29 .loc 1 64 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 8
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
34 0000 82B0 sub sp, sp, #8
35 .LCFI0:
36 .cfi_def_cfa_offset 8
65:Src/stm32f4xx_hal_msp.c ****
66:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
67:Src/stm32f4xx_hal_msp.c ****
68:Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 0 */
69:Src/stm32f4xx_hal_msp.c ****
70:Src/stm32f4xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
37 .loc 1 70 3 view .LVU1
38 .LBB2:
39 .loc 1 70 3 view .LVU2
40 0002 0021 movs r1, #0
41 0004 0091 str r1, [sp]
42 .loc 1 70 3 view .LVU3
43 0006 0B4B ldr r3, .L3
44 0008 5A6C ldr r2, [r3, #68]
45 000a 42F48042 orr r2, r2, #16384
ARM GAS /tmp/ccI17HJx.s page 3
46 000e 5A64 str r2, [r3, #68]
47 .loc 1 70 3 view .LVU4
48 0010 5A6C ldr r2, [r3, #68]
49 0012 02F48042 and r2, r2, #16384
50 0016 0092 str r2, [sp]
51 .loc 1 70 3 view .LVU5
52 0018 009A ldr r2, [sp]
53 .LBE2:
54 .loc 1 70 3 view .LVU6
71:Src/stm32f4xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
55 .loc 1 71 3 view .LVU7
56 .LBB3:
57 .loc 1 71 3 view .LVU8
58 001a 0191 str r1, [sp, #4]
59 .loc 1 71 3 view .LVU9
60 001c 1A6C ldr r2, [r3, #64]
61 001e 42F08052 orr r2, r2, #268435456
62 0022 1A64 str r2, [r3, #64]
63 .loc 1 71 3 view .LVU10
64 0024 1B6C ldr r3, [r3, #64]
65 0026 03F08053 and r3, r3, #268435456
66 002a 0193 str r3, [sp, #4]
67 .loc 1 71 3 view .LVU11
68 002c 019B ldr r3, [sp, #4]
69 .LBE3:
70 .loc 1 71 3 view .LVU12
72:Src/stm32f4xx_hal_msp.c ****
73:Src/stm32f4xx_hal_msp.c **** /* System interrupt init*/
74:Src/stm32f4xx_hal_msp.c ****
75:Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
76:Src/stm32f4xx_hal_msp.c ****
77:Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 1 */
78:Src/stm32f4xx_hal_msp.c **** }
71 .loc 1 78 1 is_stmt 0 view .LVU13
72 002e 02B0 add sp, sp, #8
73 .LCFI1:
74 .cfi_def_cfa_offset 0
75 @ sp needed
76 0030 7047 bx lr
77 .L4:
78 0032 00BF .align 2
79 .L3:
80 0034 00380240 .word 1073887232
81 .cfi_endproc
82 .LFE134:
84 .text
85 .Letext0:
86 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
87 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
88 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
ARM GAS /tmp/ccI17HJx.s page 4
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_hal_msp.c
/tmp/ccI17HJx.s:20 .text.HAL_MspInit:0000000000000000 $t
/tmp/ccI17HJx.s:26 .text.HAL_MspInit:0000000000000000 HAL_MspInit
/tmp/ccI17HJx.s:80 .text.HAL_MspInit:0000000000000034 $d
NO UNDEFINED SYMBOLS

1412
build/stm32f4xx_hal_pwr.lst Normal file
View File

File diff suppressed because it is too large Load Diff

659
build/stm32f4xx_hal_pwr_ex.lst Normal file
View File

@ -0,0 +1,659 @@
ARM GAS /tmp/ccBSoraS.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_pwr_ex.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.HAL_PWREx_EnableBkUpReg,"ax",%progbits
20 .align 1
21 .global HAL_PWREx_EnableBkUpReg
22 .syntax unified
23 .thumb
24 .thumb_func
26 HAL_PWREx_EnableBkUpReg:
27 .LFB134:
28 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c"
1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ******************************************************************************
3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @file stm32f4xx_hal_pwr_ex.c
4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @author MCD Application Team
5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver.
6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * functionalities of PWR extension peripheral:
8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * + Peripheral Extended features functions
9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *
10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ******************************************************************************
11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @attention
12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *
13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * Copyright (c) 2017 STMicroelectronics.
14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * All rights reserved.
15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *
16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * This software is licensed under terms that can be found in the LICENSE file in
17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * the root directory of this software component.
18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ******************************************************************************
20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #include "stm32f4xx_hal.h"
24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /** @addtogroup STM32F4xx_HAL_Driver
26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @{
27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief PWR HAL module driver
ARM GAS /tmp/ccBSoraS.s page 2
31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @{
32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants
39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @{
40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #define PWR_BKPREG_TIMEOUT_VALUE 1000U
44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #define PWR_VOSRDY_TIMEOUT_VALUE 1000U
45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @}
47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/
54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @{
56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Peripheral Extended features functions
60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *
61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** @verbatim
62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ===============================================================================
64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ##### Peripheral extended features functions #####
65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ===============================================================================
66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *** Main and Backup Regulators configuration ***
68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** ================================================
69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** [..]
70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** retained even in Standby or VBAT mode when the low power backup regulator
73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** is enabled. It can be considered as an internal EEPROM when VBAT is
74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** always present. You can use the HAL_PWREx_EnableBkUpReg() function to
75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** enable the low power backup regulator.
76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** save battery life.
80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** protected to prevent confidential data, such as cryptographic private
83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** key, from being accessed. The backup SRAM can be erased only through
84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** the Flash interface when a protection level change from level 1 to
85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** level 0 is requested.
86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** -@- Refer to the description of Read protection (RDP) in the Flash
87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** programming manual.
ARM GAS /tmp/ccBSoraS.s page 3
88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to have a tradeoff between
90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** performance and power consumption when the device does not operate at
91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** macro which configure VOS bit in PWR_CR register
93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** Refer to the product datasheets for more details.
95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *** FLASH Power Down configuration ****
97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** =======================================
98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** [..]
99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) By setting the FPDS bit in the PWR_CR register by using the
100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** down mode when the device enters Stop mode. When the Flash memory
102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** is in power down mode, an additional startup delay is incurred when
103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** waking up from Stop mode.
104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when
106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** is OFF and the HSI or HSE clock source is selected as system clock.
107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** The new value programmed is active only when the PLL is ON.
108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** When the PLL is OFF, the voltage scale 3 is automatically selected.
109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** Refer to the datasheets for more details.
110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *** Over-Drive and Under-Drive configuration ****
112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** =================================================
113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** [..]
114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** 2 operating modes available:
116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** voltage scaling (scale 1, scale 2 or scale 3)
118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** higher frequency than the normal mode for a given voltage scaling (scale 1,
120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function
121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mod
122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** the sequence described in Reference manual.
123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low
125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** supplies a low power voltage to the 1.2V domain, thus preserving the content of register
126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** and internal SRAM. 2 operating modes are available:
127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** available when the main regulator or the low power regulator is used in Scale 3 or
129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** low voltage mode.
130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is
131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** available when the main regulator or the low power regulator is in low voltage mode.
132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** @endverbatim
134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @{
135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Enables the Backup Regulator.
139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval HAL status
140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
29 .loc 1 142 1 view -0
30 .cfi_startproc
ARM GAS /tmp/ccBSoraS.s page 4
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 10B5 push {r4, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 4, -8
37 .cfi_offset 14, -4
143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** uint32_t tickstart = 0U;
38 .loc 1 143 3 view .LVU1
39 .LVL0:
144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
40 .loc 1 145 3 view .LVU2
41 .loc 1 145 33 is_stmt 0 view .LVU3
42 0002 0B4B ldr r3, .L8
43 0004 0122 movs r2, #1
44 0006 C3F8A420 str r2, [r3, #164]
146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Get tick */
148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** tickstart = HAL_GetTick();
45 .loc 1 148 3 is_stmt 1 view .LVU4
46 .loc 1 148 15 is_stmt 0 view .LVU5
47 000a FFF7FEFF bl HAL_GetTick
48 .LVL1:
49 000e 0446 mov r4, r0
50 .LVL2:
149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */
151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
51 .loc 1 151 3 is_stmt 1 view .LVU6
52 .L2:
53 .loc 1 151 8 view .LVU7
54 .loc 1 151 9 is_stmt 0 view .LVU8
55 0010 084B ldr r3, .L8+4
56 0012 5B68 ldr r3, [r3, #4]
57 .loc 1 151 8 view .LVU9
58 0014 13F0080F tst r3, #8
59 0018 07D1 bne .L7
152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
60 .loc 1 153 5 is_stmt 1 view .LVU10
61 .loc 1 153 9 is_stmt 0 view .LVU11
62 001a FFF7FEFF bl HAL_GetTick
63 .LVL3:
64 .loc 1 153 23 view .LVU12
65 001e 001B subs r0, r0, r4
66 .loc 1 153 7 view .LVU13
67 0020 B0F57A7F cmp r0, #1000
68 0024 F4D9 bls .L2
154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_TIMEOUT;
69 .loc 1 155 14 view .LVU14
70 0026 0320 movs r0, #3
71 0028 00E0 b .L3
72 .L7:
156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
ARM GAS /tmp/ccBSoraS.s page 5
158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_OK;
73 .loc 1 158 10 view .LVU15
74 002a 0020 movs r0, #0
75 .L3:
159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
76 .loc 1 159 1 view .LVU16
77 002c 10BD pop {r4, pc}
78 .LVL4:
79 .L9:
80 .loc 1 159 1 view .LVU17
81 002e 00BF .align 2
82 .L8:
83 0030 00000E42 .word 1108213760
84 0034 00700040 .word 1073770496
85 .cfi_endproc
86 .LFE134:
88 .section .text.HAL_PWREx_DisableBkUpReg,"ax",%progbits
89 .align 1
90 .global HAL_PWREx_DisableBkUpReg
91 .syntax unified
92 .thumb
93 .thumb_func
95 HAL_PWREx_DisableBkUpReg:
96 .LFB135:
160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Disables the Backup Regulator.
163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval HAL status
164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
97 .loc 1 166 1 is_stmt 1 view -0
98 .cfi_startproc
99 @ args = 0, pretend = 0, frame = 0
100 @ frame_needed = 0, uses_anonymous_args = 0
101 0000 10B5 push {r4, lr}
102 .LCFI1:
103 .cfi_def_cfa_offset 8
104 .cfi_offset 4, -8
105 .cfi_offset 14, -4
167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** uint32_t tickstart = 0U;
106 .loc 1 167 3 view .LVU19
107 .LVL5:
168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
108 .loc 1 169 3 view .LVU20
109 .loc 1 169 33 is_stmt 0 view .LVU21
110 0002 0B4B ldr r3, .L17
111 0004 0022 movs r2, #0
112 0006 C3F8A420 str r2, [r3, #164]
170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Get tick */
172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** tickstart = HAL_GetTick();
113 .loc 1 172 3 is_stmt 1 view .LVU22
114 .loc 1 172 15 is_stmt 0 view .LVU23
115 000a FFF7FEFF bl HAL_GetTick
116 .LVL6:
ARM GAS /tmp/ccBSoraS.s page 6
117 000e 0446 mov r4, r0
118 .LVL7:
173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */
175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
119 .loc 1 175 3 is_stmt 1 view .LVU24
120 .L11:
121 .loc 1 175 8 view .LVU25
122 .loc 1 175 9 is_stmt 0 view .LVU26
123 0010 084B ldr r3, .L17+4
124 0012 5B68 ldr r3, [r3, #4]
125 .loc 1 175 8 view .LVU27
126 0014 13F0080F tst r3, #8
127 0018 07D0 beq .L16
176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
128 .loc 1 177 5 is_stmt 1 view .LVU28
129 .loc 1 177 9 is_stmt 0 view .LVU29
130 001a FFF7FEFF bl HAL_GetTick
131 .LVL8:
132 .loc 1 177 23 view .LVU30
133 001e 001B subs r0, r0, r4
134 .loc 1 177 7 view .LVU31
135 0020 B0F57A7F cmp r0, #1000
136 0024 F4D9 bls .L11
178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_TIMEOUT;
137 .loc 1 179 14 view .LVU32
138 0026 0320 movs r0, #3
139 0028 00E0 b .L12
140 .L16:
180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_OK;
141 .loc 1 182 10 view .LVU33
142 002a 0020 movs r0, #0
143 .L12:
183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
144 .loc 1 183 1 view .LVU34
145 002c 10BD pop {r4, pc}
146 .LVL9:
147 .L18:
148 .loc 1 183 1 view .LVU35
149 002e 00BF .align 2
150 .L17:
151 0030 00000E42 .word 1108213760
152 0034 00700040 .word 1073770496
153 .cfi_endproc
154 .LFE135:
156 .section .text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits
157 .align 1
158 .global HAL_PWREx_EnableFlashPowerDown
159 .syntax unified
160 .thumb
161 .thumb_func
163 HAL_PWREx_EnableFlashPowerDown:
164 .LFB136:
ARM GAS /tmp/ccBSoraS.s page 7
184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Enables the Flash Power Down in Stop mode.
187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval None
188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown(void)
190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
165 .loc 1 190 1 is_stmt 1 view -0
166 .cfi_startproc
167 @ args = 0, pretend = 0, frame = 0
168 @ frame_needed = 0, uses_anonymous_args = 0
169 @ link register save eliminated.
191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
170 .loc 1 191 3 view .LVU37
171 .loc 1 191 33 is_stmt 0 view .LVU38
172 0000 014B ldr r3, .L20
173 0002 0122 movs r2, #1
174 0004 5A62 str r2, [r3, #36]
192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
175 .loc 1 192 1 view .LVU39
176 0006 7047 bx lr
177 .L21:
178 .align 2
179 .L20:
180 0008 00000E42 .word 1108213760
181 .cfi_endproc
182 .LFE136:
184 .section .text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits
185 .align 1
186 .global HAL_PWREx_DisableFlashPowerDown
187 .syntax unified
188 .thumb
189 .thumb_func
191 HAL_PWREx_DisableFlashPowerDown:
192 .LFB137:
193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Disables the Flash Power Down in Stop mode.
196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval None
197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown(void)
199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
193 .loc 1 199 1 is_stmt 1 view -0
194 .cfi_startproc
195 @ args = 0, pretend = 0, frame = 0
196 @ frame_needed = 0, uses_anonymous_args = 0
197 @ link register save eliminated.
200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
198 .loc 1 200 3 view .LVU41
199 .loc 1 200 33 is_stmt 0 view .LVU42
200 0000 014B ldr r3, .L23
201 0002 0022 movs r2, #0
202 0004 5A62 str r2, [r3, #36]
201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
203 .loc 1 201 1 view .LVU43
204 0006 7047 bx lr
205 .L24:
ARM GAS /tmp/ccBSoraS.s page 8
206 .align 2
207 .L23:
208 0008 00000E42 .word 1108213760
209 .cfi_endproc
210 .LFE137:
212 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits
213 .align 1
214 .global HAL_PWREx_GetVoltageRange
215 .syntax unified
216 .thumb
217 .thumb_func
219 HAL_PWREx_GetVoltageRange:
220 .LFB138:
202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Return Voltage Scaling Range.
205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval The configured scale for the regulator voltage(VOS bit field).
206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * The returned value can be one of the following:
207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void)
212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
221 .loc 1 212 1 is_stmt 1 view -0
222 .cfi_startproc
223 @ args = 0, pretend = 0, frame = 0
224 @ frame_needed = 0, uses_anonymous_args = 0
225 @ link register save eliminated.
213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return (PWR->CR & PWR_CR_VOS);
226 .loc 1 213 3 view .LVU45
227 .loc 1 213 14 is_stmt 0 view .LVU46
228 0000 024B ldr r3, .L26
229 0002 1868 ldr r0, [r3]
214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
230 .loc 1 214 1 view .LVU47
231 0004 00F48040 and r0, r0, #16384
232 0008 7047 bx lr
233 .L27:
234 000a 00BF .align 2
235 .L26:
236 000c 00700040 .word 1073770496
237 .cfi_endproc
238 .LFE138:
240 .section .text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits
241 .align 1
242 .global HAL_PWREx_ControlVoltageScaling
243 .syntax unified
244 .thumb
245 .thumb_func
247 HAL_PWREx_ControlVoltageScaling:
248 .LVL10:
249 .LFB139:
215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /**
218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @brief Configures the main internal regulator output voltage.
ARM GAS /tmp/ccBSoraS.s page 9
219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @param VoltageScaling specifies the regulator output voltage to achieve
220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * a tradeoff between performance and power consumption.
221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * the maximum value of fHCLK = 168 MHz.
224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * the maximum value of fHCLK = 144 MHz.
226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * When moving from Range 2 to Range 1, the system frequency can be increased to
229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** * @retval HAL Status
231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** */
232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
250 .loc 1 233 1 is_stmt 1 view -0
251 .cfi_startproc
252 @ args = 0, pretend = 0, frame = 8
253 @ frame_needed = 0, uses_anonymous_args = 0
254 .loc 1 233 1 is_stmt 0 view .LVU49
255 0000 10B5 push {r4, lr}
256 .LCFI2:
257 .cfi_def_cfa_offset 8
258 .cfi_offset 4, -8
259 .cfi_offset 14, -4
260 0002 82B0 sub sp, sp, #8
261 .LCFI3:
262 .cfi_def_cfa_offset 16
234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** uint32_t tickstart = 0U;
263 .loc 1 234 3 is_stmt 1 view .LVU50
264 .LVL11:
235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
265 .loc 1 236 3 view .LVU51
237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Enable PWR RCC Clock Peripheral */
239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** __HAL_RCC_PWR_CLK_ENABLE();
266 .loc 1 239 3 view .LVU52
267 .LBB2:
268 .loc 1 239 3 view .LVU53
269 0004 0024 movs r4, #0
270 0006 0094 str r4, [sp]
271 .loc 1 239 3 view .LVU54
272 0008 144A ldr r2, .L35
273 000a 116C ldr r1, [r2, #64]
274 000c 41F08051 orr r1, r1, #268435456
275 0010 1164 str r1, [r2, #64]
276 .loc 1 239 3 view .LVU55
277 0012 126C ldr r2, [r2, #64]
278 0014 02F08052 and r2, r2, #268435456
279 0018 0092 str r2, [sp]
280 .loc 1 239 3 view .LVU56
281 001a 009B ldr r3, [sp]
282 .LBE2:
283 .loc 1 239 3 view .LVU57
240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Set Range */
ARM GAS /tmp/ccBSoraS.s page 10
242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
284 .loc 1 242 3 view .LVU58
285 .LBB3:
286 .loc 1 242 3 view .LVU59
287 001c 0194 str r4, [sp, #4]
288 .loc 1 242 3 view .LVU60
289 001e 104A ldr r2, .L35+4
290 0020 1368 ldr r3, [r2]
291 0022 23F48043 bic r3, r3, #16384
292 0026 0343 orrs r3, r3, r0
293 0028 1360 str r3, [r2]
294 .loc 1 242 3 view .LVU61
295 002a 1368 ldr r3, [r2]
296 002c 03F48043 and r3, r3, #16384
297 0030 0193 str r3, [sp, #4]
298 .loc 1 242 3 view .LVU62
299 0032 019B ldr r3, [sp, #4]
300 .LBE3:
301 .loc 1 242 3 view .LVU63
243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** /* Get Start Tick*/
245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** tickstart = HAL_GetTick();
302 .loc 1 245 3 view .LVU64
303 .loc 1 245 15 is_stmt 0 view .LVU65
304 0034 FFF7FEFF bl HAL_GetTick
305 .LVL12:
306 .loc 1 245 15 view .LVU66
307 0038 0446 mov r4, r0
308 .LVL13:
246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
309 .loc 1 246 3 is_stmt 1 view .LVU67
310 .L29:
311 .loc 1 246 8 view .LVU68
312 .loc 1 246 10 is_stmt 0 view .LVU69
313 003a 094B ldr r3, .L35+4
314 003c 5B68 ldr r3, [r3, #4]
315 .loc 1 246 8 view .LVU70
316 003e 13F4804F tst r3, #16384
317 0042 07D1 bne .L34
247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
318 .loc 1 248 5 is_stmt 1 view .LVU71
319 .loc 1 248 9 is_stmt 0 view .LVU72
320 0044 FFF7FEFF bl HAL_GetTick
321 .LVL14:
322 .loc 1 248 23 view .LVU73
323 0048 001B subs r0, r0, r4
324 .loc 1 248 7 view .LVU74
325 004a B0F57A7F cmp r0, #1000
326 004e F4D9 bls .L29
249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** {
250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_TIMEOUT;
327 .loc 1 250 14 view .LVU75
328 0050 0320 movs r0, #3
329 0052 00E0 b .L30
330 .L34:
251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
ARM GAS /tmp/ccBSoraS.s page 11
252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c ****
254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** return HAL_OK;
331 .loc 1 254 10 view .LVU76
332 0054 0020 movs r0, #0
333 .L30:
255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c **** }
334 .loc 1 255 1 view .LVU77
335 0056 02B0 add sp, sp, #8
336 .LCFI4:
337 .cfi_def_cfa_offset 8
338 @ sp needed
339 0058 10BD pop {r4, pc}
340 .LVL15:
341 .L36:
342 .loc 1 255 1 view .LVU78
343 005a 00BF .align 2
344 .L35:
345 005c 00380240 .word 1073887232
346 0060 00700040 .word 1073770496
347 .cfi_endproc
348 .LFE139:
350 .text
351 .Letext0:
352 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
353 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
354 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
355 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
356 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
357 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/ccBSoraS.s page 12
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_hal_pwr_ex.c
/tmp/ccBSoraS.s:20 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 $t
/tmp/ccBSoraS.s:26 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 HAL_PWREx_EnableBkUpReg
/tmp/ccBSoraS.s:83 .text.HAL_PWREx_EnableBkUpReg:0000000000000030 $d
/tmp/ccBSoraS.s:89 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 $t
/tmp/ccBSoraS.s:95 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 HAL_PWREx_DisableBkUpReg
/tmp/ccBSoraS.s:151 .text.HAL_PWREx_DisableBkUpReg:0000000000000030 $d
/tmp/ccBSoraS.s:157 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 $t
/tmp/ccBSoraS.s:163 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 HAL_PWREx_EnableFlashPowerDown
/tmp/ccBSoraS.s:180 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000008 $d
/tmp/ccBSoraS.s:185 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 $t
/tmp/ccBSoraS.s:191 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 HAL_PWREx_DisableFlashPowerDown
/tmp/ccBSoraS.s:208 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000008 $d
/tmp/ccBSoraS.s:213 .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t
/tmp/ccBSoraS.s:219 .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange
/tmp/ccBSoraS.s:236 .text.HAL_PWREx_GetVoltageRange:000000000000000c $d
/tmp/ccBSoraS.s:241 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 $t
/tmp/ccBSoraS.s:247 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 HAL_PWREx_ControlVoltageScaling
/tmp/ccBSoraS.s:345 .text.HAL_PWREx_ControlVoltageScaling:000000000000005c $d
UNDEFINED SYMBOLS
HAL_GetTick

3636
build/stm32f4xx_hal_rcc.lst Normal file
View File

File diff suppressed because it is too large Load Diff

4734
build/stm32f4xx_hal_rcc_ex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

1833
build/stm32f4xx_hal_rng.lst Normal file
View File

File diff suppressed because it is too large Load Diff

5968
build/stm32f4xx_hal_rtc.lst Normal file
View File

File diff suppressed because it is too large Load Diff

5904
build/stm32f4xx_hal_rtc_ex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

28248
build/stm32f4xx_hal_tim.lst Normal file
View File

File diff suppressed because it is too large Load Diff

9868
build/stm32f4xx_hal_tim_ex.lst Normal file
View File

File diff suppressed because it is too large Load Diff

17023
build/stm32f4xx_hal_uart.lst Normal file
View File

File diff suppressed because it is too large Load Diff

685
build/stm32f4xx_hal_wwdg.lst Normal file
View File

@ -0,0 +1,685 @@
ARM GAS /tmp/ccTjX6jT.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_wwdg.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.HAL_WWDG_MspInit,"ax",%progbits
20 .align 1
21 .weak HAL_WWDG_MspInit
22 .syntax unified
23 .thumb
24 .thumb_func
26 HAL_WWDG_MspInit:
27 .LVL0:
28 .LFB135:
29 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c"
1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ******************************************************************************
3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @file stm32f4xx_hal_wwdg.c
4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @author MCD Application Team
5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief WWDG HAL module driver.
6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * functionalities of the Window Watchdog (WWDG) peripheral:
8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * + Initialization and Configuration functions
9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * + IO operation functions
10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ******************************************************************************
11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @attention
12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *
13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * Copyright (c) 2016 STMicroelectronics.
14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * All rights reserved.
15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *
16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * This software is licensed under terms that can be found in the LICENSE file
17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * in the root directory of this software component.
18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *
20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ******************************************************************************
21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @verbatim
22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ##### WWDG Specific features #####
24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** Once enabled the WWDG generates a system reset on expiry of a programmed
27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** time period, unless the program refreshes the counter (T[6;0] downcounter)
28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** before reaching 0x3F value (i.e. a reset is generated when the counter
29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** value rolls down from 0x40 to 0x3F).
ARM GAS /tmp/ccTjX6jT.s page 2
30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) An MCU reset is also generated if the counter value is refreshed
32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** before the counter has reached the refresh window value. This
33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** implies that the counter must be refreshed in a limited window.
34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Once enabled the WWDG cannot be disabled except by a system reset.
35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) If required by application, an Early Wakeup Interrupt can be triggered
36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** in order to be warned before WWDG expiration. The Early Wakeup Interrupt
37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (EWI) can be used if specific safety operations or data logging must
38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** be performed before the actual reset is generated. When the downcounter
39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** disabled except by a system reset.
42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** reset occurs.
44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) The WWDG counter input clock is derived from the APB clock divided
45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** by a programmable prescaler.
46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** where T[5;0] are the lowest 6 bits of Counter.
49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) WWDG Counter refresh is allowed between the following limits :
50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Typical values:
53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) Counter min (T[5;0] = 0x00) at 42MHz (PCLK1) with zero prescaler:
54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** max timeout before reset: approximately 97.52us
55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) Counter max (T[5;0] = 0x3F) at 42MHz (PCLK1) with prescaler
56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** dividing by 8:
57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** max timeout before reset: approximately 49.93ms
58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ##### How to use this driver #####
60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *** Common driver usage ***
63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ===========================
64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Configure the WWDG prescaler, refresh window value, counter value and early
68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** interrupt status using HAL_WWDG_Init() function. This will automatically
69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** enable WWDG and start its downcounter. Time reference can be taken from
70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** function exit. Care must be taken to provide a counter value
71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** greater than 0x40 to prevent generation of immediate reset.
72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** triggered by the interrupt service routine, flag will be automatically
75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** can add his own code by customization of callback HAL_WWDG_WakeupCallback.
77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Then the application program must refresh the WWDG counter at regular
78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** intervals during normal operation to prevent an MCU reset, using
79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_WWDG_Refresh() function. This operation must occur only when
80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** the counter is lower than the refresh window value already programmed.
81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *** Callback registration ***
83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** =============================
84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
ARM GAS /tmp/ccTjX6jT.s page 3
87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** the user to configure dynamically the driver callbacks. Use Functions
88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_WWDG_RegisterCallback() to register a user callback.
89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Function HAL_WWDG_RegisterCallback() allows to register following
91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** callbacks:
92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) EwiCallback : callback for Early WakeUp Interrupt.
93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) MspInitCallback : WWDG MspInit.
94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** This function takes as parameters the HAL peripheral handle, the Callback ID
95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** and a pointer to the user callback function.
96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** the default weak function. HAL_WWDG_UnRegisterCallback()
99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** takes as parameters the HAL peripheral handle and the Callback ID.
100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** This function allows to reset following callbacks:
101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) EwiCallback : callback for Early WakeUp Interrupt.
102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (++) MspInitCallback : WWDG MspInit.
103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** When calling HAL_WWDG_Init function, callbacks are reset to the
106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** corresponding legacy weak functions:
107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** not been registered before.
109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** not defined, the callback registering feature is not available
113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** and weak (overridden) callbacks are used.
114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *** WWDG HAL driver macros list ***
116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ===================================
117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** Below the list of available macros in WWDG HAL driver.
119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @endverbatim
125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Includes ------------------------------------------------------------------*/
128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #include "stm32f4xx_hal.h"
129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /** @addtogroup STM32F4xx_HAL_Driver
131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @{
132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #ifdef HAL_WWDG_MODULE_ENABLED
135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /** @defgroup WWDG WWDG
136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief WWDG HAL module driver.
137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @{
138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Private typedef -----------------------------------------------------------*/
141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Private define ------------------------------------------------------------*/
142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Private macro -------------------------------------------------------------*/
143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Private variables ---------------------------------------------------------*/
ARM GAS /tmp/ccTjX6jT.s page 4
144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Private function prototypes -----------------------------------------------*/
145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Exported functions --------------------------------------------------------*/
146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @{
149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Initialization and Configuration functions.
153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *
154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @verbatim
155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ##### Initialization and Configuration functions #####
157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** This section provides functions allowing to:
160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Initialize and start the WWDG according to the specified parameters
161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** in the WWDG_InitTypeDef of associated handle.
162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Initialize the WWDG MSP.
163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @endverbatim
165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @{
166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Initialize the WWDG according to the specified.
170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * parameters in the WWDG_InitTypeDef of associated handle.
171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * the configuration information for the specified WWDG module.
173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval HAL status
174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check the WWDG handle allocation */
178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (hwwdg == NULL)
179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** return HAL_ERROR;
181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check the parameters */
184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Reset Callback pointers */
192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (hwwdg->EwiCallback == NULL)
193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (hwwdg->MspInitCallback == NULL)
198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->MspInitCallback = HAL_WWDG_MspInit;
200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
ARM GAS /tmp/ccTjX6jT.s page 5
201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Init the low level hardware */
203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->MspInitCallback(hwwdg);
204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #else
205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Init the low level hardware */
206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_WWDG_MspInit(hwwdg);
207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Set WWDG Counter */
210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Set WWDG Prescaler and Window */
213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window
214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Return function status */
216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** return HAL_OK;
217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Initialize the WWDG MSP.
222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * the configuration information for the specified WWDG module.
224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @note When rewriting this function in user file, mechanism may be added
225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * to avoid multiple initialize when HAL_WWDG_Init function is called
226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * again to change parameters.
227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval None
228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
30 .loc 1 230 1 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Prevent unused argument(s) compilation warning */
232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** UNUSED(hwwdg);
35 .loc 1 232 3 view .LVU1
233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* NOTE: This function should not be modified, when the callback is needed,
235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** the HAL_WWDG_MspInit could be implemented in the user file
236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
36 .loc 1 237 1 is_stmt 0 view .LVU2
37 0000 7047 bx lr
38 .cfi_endproc
39 .LFE135:
41 .section .text.HAL_WWDG_Init,"ax",%progbits
42 .align 1
43 .global HAL_WWDG_Init
44 .syntax unified
45 .thumb
46 .thumb_func
48 HAL_WWDG_Init:
49 .LVL1:
50 .LFB134:
176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check the WWDG handle allocation */
ARM GAS /tmp/ccTjX6jT.s page 6
51 .loc 1 176 1 is_stmt 1 view -0
52 .cfi_startproc
53 @ args = 0, pretend = 0, frame = 0
54 @ frame_needed = 0, uses_anonymous_args = 0
178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
55 .loc 1 178 3 view .LVU4
178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
56 .loc 1 178 6 is_stmt 0 view .LVU5
57 0000 88B1 cbz r0, .L4
176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check the WWDG handle allocation */
58 .loc 1 176 1 view .LVU6
59 0002 10B5 push {r4, lr}
60 .LCFI0:
61 .cfi_def_cfa_offset 8
62 .cfi_offset 4, -8
63 .cfi_offset 14, -4
64 0004 0446 mov r4, r0
184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
65 .loc 1 184 3 is_stmt 1 view .LVU7
185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
66 .loc 1 185 3 view .LVU8
186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
67 .loc 1 186 3 view .LVU9
187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
68 .loc 1 187 3 view .LVU10
188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
69 .loc 1 188 3 view .LVU11
206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
70 .loc 1 206 3 view .LVU12
71 0006 FFF7FEFF bl HAL_WWDG_MspInit
72 .LVL2:
210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
73 .loc 1 210 3 view .LVU13
74 000a E368 ldr r3, [r4, #12]
75 000c 2268 ldr r2, [r4]
76 000e 43F08003 orr r3, r3, #128
77 0012 1360 str r3, [r2]
213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
78 .loc 1 213 3 view .LVU14
79 0014 2369 ldr r3, [r4, #16]
80 0016 6268 ldr r2, [r4, #4]
81 0018 1343 orrs r3, r3, r2
82 001a A168 ldr r1, [r4, #8]
83 001c 2268 ldr r2, [r4]
84 001e 0B43 orrs r3, r3, r1
85 0020 5360 str r3, [r2, #4]
216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
86 .loc 1 216 3 view .LVU15
216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
87 .loc 1 216 10 is_stmt 0 view .LVU16
88 0022 0020 movs r0, #0
217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
89 .loc 1 217 1 view .LVU17
90 0024 10BD pop {r4, pc}
91 .LVL3:
92 .L4:
93 .LCFI1:
ARM GAS /tmp/ccTjX6jT.s page 7
94 .cfi_def_cfa_offset 0
95 .cfi_restore 4
96 .cfi_restore 14
180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
97 .loc 1 180 12 view .LVU18
98 0026 0120 movs r0, #1
99 .LVL4:
217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
100 .loc 1 217 1 view .LVU19
101 0028 7047 bx lr
102 .cfi_endproc
103 .LFE134:
105 .section .text.HAL_WWDG_Refresh,"ax",%progbits
106 .align 1
107 .global HAL_WWDG_Refresh
108 .syntax unified
109 .thumb
110 .thumb_func
112 HAL_WWDG_Refresh:
113 .LVL5:
114 .LFB136:
238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Register a User WWDG Callback
243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * To be used instead of the weak (overridden) predefined callback
244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg WWDG handle
245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param CallbackID ID of the callback to be registered
246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * This parameter can be one of the following values:
247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param pCallback pointer to the Callback function
250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval status
251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef C
253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** pWWDG_CallbackTypeDef pCallback)
254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef status = HAL_OK;
256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (pCallback == NULL)
258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** status = HAL_ERROR;
260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** else
262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** switch (CallbackID)
264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** case HAL_WWDG_EWI_CB_ID:
266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->EwiCallback = pCallback;
267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** case HAL_WWDG_MSPINIT_CB_ID:
270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->MspInitCallback = pCallback;
271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** default:
ARM GAS /tmp/ccTjX6jT.s page 8
274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** status = HAL_ERROR;
275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** return status;
280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Unregister a WWDG Callback
285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * WWDG Callback is redirected to the weak (overridden) predefined callback
286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg WWDG handle
287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param CallbackID ID of the callback to be registered
288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * This parameter can be one of the following values:
289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval status
292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef
294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef status = HAL_OK;
296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** switch (CallbackID)
298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** case HAL_WWDG_EWI_CB_ID:
300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** case HAL_WWDG_MSPINIT_CB_ID:
304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->MspInitCallback = HAL_WWDG_MspInit;
305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** default:
308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** status = HAL_ERROR;
309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** break;
310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** return status;
313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @}
318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief IO operation functions
322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** *
323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @verbatim
324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ##### IO operation functions #####
326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** ==============================================================================
327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** [..]
328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** This section provides functions allowing to:
329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Refresh the WWDG.
330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** (+) Handle WWDG interrupt request and associated function callback.
ARM GAS /tmp/ccTjX6jT.s page 9
331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** @endverbatim
333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @{
334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Refresh the WWDG.
338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * the configuration information for the specified WWDG module.
340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval HAL status
341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
115 .loc 1 343 1 is_stmt 1 view -0
116 .cfi_startproc
117 @ args = 0, pretend = 0, frame = 0
118 @ frame_needed = 0, uses_anonymous_args = 0
119 @ link register save eliminated.
344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Write to WWDG CR the WWDG Counter value to refresh with */
345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
120 .loc 1 345 3 view .LVU21
121 0000 0368 ldr r3, [r0]
122 0002 C268 ldr r2, [r0, #12]
123 0004 1A60 str r2, [r3]
346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Return function status */
348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** return HAL_OK;
124 .loc 1 348 3 view .LVU22
349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
125 .loc 1 349 1 is_stmt 0 view .LVU23
126 0006 0020 movs r0, #0
127 .LVL6:
128 .loc 1 349 1 view .LVU24
129 0008 7047 bx lr
130 .cfi_endproc
131 .LFE136:
133 .section .text.HAL_WWDG_EarlyWakeupCallback,"ax",%progbits
134 .align 1
135 .weak HAL_WWDG_EarlyWakeupCallback
136 .syntax unified
137 .thumb
138 .thumb_func
140 HAL_WWDG_EarlyWakeupCallback:
141 .LVL7:
142 .LFB138:
350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief Handle WWDG interrupt request.
353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * or data logging must be performed before the actual reset is generated.
355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * EWIMode set to WWDG_EWI_ENABLE.
357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * When the downcounter reaches the value 0x40, and EWI interrupt is
358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * generated and the corresponding Interrupt Service Routine (ISR) can
359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * be used to trigger specific actions (such as communications or data
360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * logging), before resetting the device.
361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
ARM GAS /tmp/ccTjX6jT.s page 10
362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * the configuration information for the specified WWDG module.
363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval None
364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check if Early Wakeup Interrupt is enable */
368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check if WWDG Early Wakeup Interrupt occurred */
371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Clear the WWDG Early Wakeup flag */
374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Early Wakeup registered callback */
378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** hwwdg->EwiCallback(hwwdg);
379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #else
380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Early Wakeup callback */
381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** HAL_WWDG_EarlyWakeupCallback(hwwdg);
382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /**
389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @brief WWDG Early Wakeup callback.
390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * the configuration information for the specified WWDG module.
392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** * @retval None
393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
143 .loc 1 395 1 is_stmt 1 view -0
144 .cfi_startproc
145 @ args = 0, pretend = 0, frame = 0
146 @ frame_needed = 0, uses_anonymous_args = 0
147 @ link register save eliminated.
396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Prevent unused argument(s) compilation warning */
397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** UNUSED(hwwdg);
148 .loc 1 397 3 view .LVU26
398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* NOTE: This function should not be modified, when the callback is needed,
400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** */
402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** }
149 .loc 1 402 1 is_stmt 0 view .LVU27
150 0000 7047 bx lr
151 .cfi_endproc
152 .LFE138:
154 .section .text.HAL_WWDG_IRQHandler,"ax",%progbits
155 .align 1
156 .global HAL_WWDG_IRQHandler
157 .syntax unified
158 .thumb
159 .thumb_func
ARM GAS /tmp/ccTjX6jT.s page 11
161 HAL_WWDG_IRQHandler:
162 .LVL8:
163 .LFB137:
366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check if Early Wakeup Interrupt is enable */
164 .loc 1 366 1 is_stmt 1 view -0
165 .cfi_startproc
166 @ args = 0, pretend = 0, frame = 0
167 @ frame_needed = 0, uses_anonymous_args = 0
366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** /* Check if Early Wakeup Interrupt is enable */
168 .loc 1 366 1 is_stmt 0 view .LVU29
169 0000 08B5 push {r3, lr}
170 .LCFI2:
171 .cfi_def_cfa_offset 8
172 .cfi_offset 3, -8
173 .cfi_offset 14, -4
368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
174 .loc 1 368 3 is_stmt 1 view .LVU30
368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
175 .loc 1 368 7 is_stmt 0 view .LVU31
176 0002 0368 ldr r3, [r0]
177 0004 5A68 ldr r2, [r3, #4]
368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
178 .loc 1 368 6 view .LVU32
179 0006 12F4007F tst r2, #512
180 000a 03D0 beq .L11
371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
181 .loc 1 371 5 is_stmt 1 view .LVU33
371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
182 .loc 1 371 9 is_stmt 0 view .LVU34
183 000c 9A68 ldr r2, [r3, #8]
371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** {
184 .loc 1 371 8 view .LVU35
185 000e 12F0010F tst r2, #1
186 0012 00D1 bne .L14
187 .LVL9:
188 .L11:
385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
189 .loc 1 385 1 view .LVU36
190 0014 08BD pop {r3, pc}
191 .LVL10:
192 .L14:
374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
193 .loc 1 374 7 is_stmt 1 view .LVU37
194 0016 6FF00102 mvn r2, #1
195 001a 9A60 str r2, [r3, #8]
381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c **** #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
196 .loc 1 381 7 view .LVU38
197 001c FFF7FEFF bl HAL_WWDG_EarlyWakeupCallback
198 .LVL11:
385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c ****
199 .loc 1 385 1 is_stmt 0 view .LVU39
200 0020 F8E7 b .L11
201 .cfi_endproc
202 .LFE137:
204 .text
205 .Letext0:
206 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
ARM GAS /tmp/ccTjX6jT.s page 12
207 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
208 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
209 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
210 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
211 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h"
ARM GAS /tmp/ccTjX6jT.s page 13
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_hal_wwdg.c
/tmp/ccTjX6jT.s:20 .text.HAL_WWDG_MspInit:0000000000000000 $t
/tmp/ccTjX6jT.s:26 .text.HAL_WWDG_MspInit:0000000000000000 HAL_WWDG_MspInit
/tmp/ccTjX6jT.s:42 .text.HAL_WWDG_Init:0000000000000000 $t
/tmp/ccTjX6jT.s:48 .text.HAL_WWDG_Init:0000000000000000 HAL_WWDG_Init
/tmp/ccTjX6jT.s:106 .text.HAL_WWDG_Refresh:0000000000000000 $t
/tmp/ccTjX6jT.s:112 .text.HAL_WWDG_Refresh:0000000000000000 HAL_WWDG_Refresh
/tmp/ccTjX6jT.s:134 .text.HAL_WWDG_EarlyWakeupCallback:0000000000000000 $t
/tmp/ccTjX6jT.s:140 .text.HAL_WWDG_EarlyWakeupCallback:0000000000000000 HAL_WWDG_EarlyWakeupCallback
/tmp/ccTjX6jT.s:155 .text.HAL_WWDG_IRQHandler:0000000000000000 $t
/tmp/ccTjX6jT.s:161 .text.HAL_WWDG_IRQHandler:0000000000000000 HAL_WWDG_IRQHandler
NO UNDEFINED SYMBOLS

449
build/stm32f4xx_it.lst Normal file
View File

@ -0,0 +1,449 @@
ARM GAS /tmp/cctvVj0a.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_it.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.NMI_Handler,"ax",%progbits
20 .align 1
21 .global NMI_Handler
22 .syntax unified
23 .thumb
24 .thumb_func
26 NMI_Handler:
27 .LFB134:
28 .file 1 "Src/stm32f4xx_it.c"
1:Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */
2:Src/stm32f4xx_it.c **** /**
3:Src/stm32f4xx_it.c **** ******************************************************************************
4:Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c
5:Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines.
6:Src/stm32f4xx_it.c **** ******************************************************************************
7:Src/stm32f4xx_it.c **** * @attention
8:Src/stm32f4xx_it.c **** *
9:Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics.
10:Src/stm32f4xx_it.c **** * All rights reserved.
11:Src/stm32f4xx_it.c **** *
12:Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Src/stm32f4xx_it.c **** * in the root directory of this software component.
14:Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Src/stm32f4xx_it.c **** *
16:Src/stm32f4xx_it.c **** ******************************************************************************
17:Src/stm32f4xx_it.c **** */
18:Src/stm32f4xx_it.c **** /* USER CODE END Header */
19:Src/stm32f4xx_it.c ****
20:Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/
21:Src/stm32f4xx_it.c **** #include "main.h"
22:Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h"
23:Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/
24:Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */
25:Src/stm32f4xx_it.c **** /* USER CODE END Includes */
26:Src/stm32f4xx_it.c ****
27:Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
28:Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */
29:Src/stm32f4xx_it.c ****
30:Src/stm32f4xx_it.c **** /* USER CODE END TD */
ARM GAS /tmp/cctvVj0a.s page 2
31:Src/stm32f4xx_it.c ****
32:Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/
33:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */
34:Src/stm32f4xx_it.c ****
35:Src/stm32f4xx_it.c **** /* USER CODE END PD */
36:Src/stm32f4xx_it.c ****
37:Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/
38:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */
39:Src/stm32f4xx_it.c ****
40:Src/stm32f4xx_it.c **** /* USER CODE END PM */
41:Src/stm32f4xx_it.c ****
42:Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/
43:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */
44:Src/stm32f4xx_it.c ****
45:Src/stm32f4xx_it.c **** /* USER CODE END PV */
46:Src/stm32f4xx_it.c ****
47:Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
48:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */
49:Src/stm32f4xx_it.c ****
50:Src/stm32f4xx_it.c **** /* USER CODE END PFP */
51:Src/stm32f4xx_it.c ****
52:Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/
53:Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */
54:Src/stm32f4xx_it.c ****
55:Src/stm32f4xx_it.c **** /* USER CODE END 0 */
56:Src/stm32f4xx_it.c ****
57:Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/
58:Src/stm32f4xx_it.c ****
59:Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */
60:Src/stm32f4xx_it.c ****
61:Src/stm32f4xx_it.c **** /* USER CODE END EV */
62:Src/stm32f4xx_it.c ****
63:Src/stm32f4xx_it.c **** /******************************************************************************/
64:Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
65:Src/stm32f4xx_it.c **** /******************************************************************************/
66:Src/stm32f4xx_it.c **** /**
67:Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt.
68:Src/stm32f4xx_it.c **** */
69:Src/stm32f4xx_it.c **** void NMI_Handler(void)
70:Src/stm32f4xx_it.c **** {
29 .loc 1 70 1 view -0
30 .cfi_startproc
31 @ Volatile: function does not return.
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
35 .L2:
71:Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
72:Src/stm32f4xx_it.c ****
73:Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
74:Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
75:Src/stm32f4xx_it.c **** while (1)
36 .loc 1 75 4 discriminator 1 view .LVU1
76:Src/stm32f4xx_it.c **** {
77:Src/stm32f4xx_it.c **** }
37 .loc 1 77 3 discriminator 1 view .LVU2
75:Src/stm32f4xx_it.c **** {
ARM GAS /tmp/cctvVj0a.s page 3
38 .loc 1 75 10 discriminator 1 view .LVU3
39 0000 FEE7 b .L2
40 .cfi_endproc
41 .LFE134:
43 .section .text.HardFault_Handler,"ax",%progbits
44 .align 1
45 .global HardFault_Handler
46 .syntax unified
47 .thumb
48 .thumb_func
50 HardFault_Handler:
51 .LFB135:
78:Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
79:Src/stm32f4xx_it.c **** }
80:Src/stm32f4xx_it.c ****
81:Src/stm32f4xx_it.c **** /**
82:Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt.
83:Src/stm32f4xx_it.c **** */
84:Src/stm32f4xx_it.c **** void HardFault_Handler(void)
85:Src/stm32f4xx_it.c **** {
52 .loc 1 85 1 view -0
53 .cfi_startproc
54 @ Volatile: function does not return.
55 @ args = 0, pretend = 0, frame = 0
56 @ frame_needed = 0, uses_anonymous_args = 0
57 @ link register save eliminated.
58 .L4:
86:Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
87:Src/stm32f4xx_it.c ****
88:Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
89:Src/stm32f4xx_it.c **** while (1)
59 .loc 1 89 3 discriminator 1 view .LVU5
90:Src/stm32f4xx_it.c **** {
91:Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
92:Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
93:Src/stm32f4xx_it.c **** }
60 .loc 1 93 3 discriminator 1 view .LVU6
89:Src/stm32f4xx_it.c **** {
61 .loc 1 89 9 discriminator 1 view .LVU7
62 0000 FEE7 b .L4
63 .cfi_endproc
64 .LFE135:
66 .section .text.MemManage_Handler,"ax",%progbits
67 .align 1
68 .global MemManage_Handler
69 .syntax unified
70 .thumb
71 .thumb_func
73 MemManage_Handler:
74 .LFB136:
94:Src/stm32f4xx_it.c **** }
95:Src/stm32f4xx_it.c ****
96:Src/stm32f4xx_it.c **** /**
97:Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault.
98:Src/stm32f4xx_it.c **** */
99:Src/stm32f4xx_it.c **** void MemManage_Handler(void)
100:Src/stm32f4xx_it.c **** {
ARM GAS /tmp/cctvVj0a.s page 4
75 .loc 1 100 1 view -0
76 .cfi_startproc
77 @ Volatile: function does not return.
78 @ args = 0, pretend = 0, frame = 0
79 @ frame_needed = 0, uses_anonymous_args = 0
80 @ link register save eliminated.
81 .L6:
101:Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
102:Src/stm32f4xx_it.c ****
103:Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
104:Src/stm32f4xx_it.c **** while (1)
82 .loc 1 104 3 discriminator 1 view .LVU9
105:Src/stm32f4xx_it.c **** {
106:Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
107:Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
108:Src/stm32f4xx_it.c **** }
83 .loc 1 108 3 discriminator 1 view .LVU10
104:Src/stm32f4xx_it.c **** {
84 .loc 1 104 9 discriminator 1 view .LVU11
85 0000 FEE7 b .L6
86 .cfi_endproc
87 .LFE136:
89 .section .text.BusFault_Handler,"ax",%progbits
90 .align 1
91 .global BusFault_Handler
92 .syntax unified
93 .thumb
94 .thumb_func
96 BusFault_Handler:
97 .LFB137:
109:Src/stm32f4xx_it.c **** }
110:Src/stm32f4xx_it.c ****
111:Src/stm32f4xx_it.c **** /**
112:Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
113:Src/stm32f4xx_it.c **** */
114:Src/stm32f4xx_it.c **** void BusFault_Handler(void)
115:Src/stm32f4xx_it.c **** {
98 .loc 1 115 1 view -0
99 .cfi_startproc
100 @ Volatile: function does not return.
101 @ args = 0, pretend = 0, frame = 0
102 @ frame_needed = 0, uses_anonymous_args = 0
103 @ link register save eliminated.
104 .L8:
116:Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
117:Src/stm32f4xx_it.c ****
118:Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
119:Src/stm32f4xx_it.c **** while (1)
105 .loc 1 119 3 discriminator 1 view .LVU13
120:Src/stm32f4xx_it.c **** {
121:Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
122:Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
123:Src/stm32f4xx_it.c **** }
106 .loc 1 123 3 discriminator 1 view .LVU14
119:Src/stm32f4xx_it.c **** {
107 .loc 1 119 9 discriminator 1 view .LVU15
108 0000 FEE7 b .L8
ARM GAS /tmp/cctvVj0a.s page 5
109 .cfi_endproc
110 .LFE137:
112 .section .text.UsageFault_Handler,"ax",%progbits
113 .align 1
114 .global UsageFault_Handler
115 .syntax unified
116 .thumb
117 .thumb_func
119 UsageFault_Handler:
120 .LFB138:
124:Src/stm32f4xx_it.c **** }
125:Src/stm32f4xx_it.c ****
126:Src/stm32f4xx_it.c **** /**
127:Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
128:Src/stm32f4xx_it.c **** */
129:Src/stm32f4xx_it.c **** void UsageFault_Handler(void)
130:Src/stm32f4xx_it.c **** {
121 .loc 1 130 1 view -0
122 .cfi_startproc
123 @ Volatile: function does not return.
124 @ args = 0, pretend = 0, frame = 0
125 @ frame_needed = 0, uses_anonymous_args = 0
126 @ link register save eliminated.
127 .L10:
131:Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
132:Src/stm32f4xx_it.c ****
133:Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
134:Src/stm32f4xx_it.c **** while (1)
128 .loc 1 134 3 discriminator 1 view .LVU17
135:Src/stm32f4xx_it.c **** {
136:Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
137:Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
138:Src/stm32f4xx_it.c **** }
129 .loc 1 138 3 discriminator 1 view .LVU18
134:Src/stm32f4xx_it.c **** {
130 .loc 1 134 9 discriminator 1 view .LVU19
131 0000 FEE7 b .L10
132 .cfi_endproc
133 .LFE138:
135 .section .text.SVC_Handler,"ax",%progbits
136 .align 1
137 .global SVC_Handler
138 .syntax unified
139 .thumb
140 .thumb_func
142 SVC_Handler:
143 .LFB139:
139:Src/stm32f4xx_it.c **** }
140:Src/stm32f4xx_it.c ****
141:Src/stm32f4xx_it.c **** /**
142:Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction.
143:Src/stm32f4xx_it.c **** */
144:Src/stm32f4xx_it.c **** void SVC_Handler(void)
145:Src/stm32f4xx_it.c **** {
144 .loc 1 145 1 view -0
145 .cfi_startproc
146 @ args = 0, pretend = 0, frame = 0
ARM GAS /tmp/cctvVj0a.s page 6
147 @ frame_needed = 0, uses_anonymous_args = 0
148 @ link register save eliminated.
146:Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
147:Src/stm32f4xx_it.c ****
148:Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
149:Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
150:Src/stm32f4xx_it.c ****
151:Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
152:Src/stm32f4xx_it.c **** }
149 .loc 1 152 1 view .LVU21
150 0000 7047 bx lr
151 .cfi_endproc
152 .LFE139:
154 .section .text.DebugMon_Handler,"ax",%progbits
155 .align 1
156 .global DebugMon_Handler
157 .syntax unified
158 .thumb
159 .thumb_func
161 DebugMon_Handler:
162 .LFB140:
153:Src/stm32f4xx_it.c ****
154:Src/stm32f4xx_it.c **** /**
155:Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor.
156:Src/stm32f4xx_it.c **** */
157:Src/stm32f4xx_it.c **** void DebugMon_Handler(void)
158:Src/stm32f4xx_it.c **** {
163 .loc 1 158 1 view -0
164 .cfi_startproc
165 @ args = 0, pretend = 0, frame = 0
166 @ frame_needed = 0, uses_anonymous_args = 0
167 @ link register save eliminated.
159:Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
160:Src/stm32f4xx_it.c ****
161:Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
162:Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
163:Src/stm32f4xx_it.c ****
164:Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
165:Src/stm32f4xx_it.c **** }
168 .loc 1 165 1 view .LVU23
169 0000 7047 bx lr
170 .cfi_endproc
171 .LFE140:
173 .section .text.PendSV_Handler,"ax",%progbits
174 .align 1
175 .global PendSV_Handler
176 .syntax unified
177 .thumb
178 .thumb_func
180 PendSV_Handler:
181 .LFB141:
166:Src/stm32f4xx_it.c ****
167:Src/stm32f4xx_it.c **** /**
168:Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service.
169:Src/stm32f4xx_it.c **** */
170:Src/stm32f4xx_it.c **** void PendSV_Handler(void)
171:Src/stm32f4xx_it.c **** {
ARM GAS /tmp/cctvVj0a.s page 7
182 .loc 1 171 1 view -0
183 .cfi_startproc
184 @ args = 0, pretend = 0, frame = 0
185 @ frame_needed = 0, uses_anonymous_args = 0
186 @ link register save eliminated.
172:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
173:Src/stm32f4xx_it.c ****
174:Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
175:Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
176:Src/stm32f4xx_it.c ****
177:Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
178:Src/stm32f4xx_it.c **** }
187 .loc 1 178 1 view .LVU25
188 0000 7047 bx lr
189 .cfi_endproc
190 .LFE141:
192 .section .text.SysTick_Handler,"ax",%progbits
193 .align 1
194 .global SysTick_Handler
195 .syntax unified
196 .thumb
197 .thumb_func
199 SysTick_Handler:
200 .LFB142:
179:Src/stm32f4xx_it.c ****
180:Src/stm32f4xx_it.c **** /**
181:Src/stm32f4xx_it.c **** * @brief This function handles System tick timer.
182:Src/stm32f4xx_it.c **** */
183:Src/stm32f4xx_it.c **** void SysTick_Handler(void)
184:Src/stm32f4xx_it.c **** {
201 .loc 1 184 1 view -0
202 .cfi_startproc
203 @ args = 0, pretend = 0, frame = 0
204 @ frame_needed = 0, uses_anonymous_args = 0
205 0000 08B5 push {r3, lr}
206 .LCFI0:
207 .cfi_def_cfa_offset 8
208 .cfi_offset 3, -8
209 .cfi_offset 14, -4
185:Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
186:Src/stm32f4xx_it.c ****
187:Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
188:Src/stm32f4xx_it.c **** HAL_IncTick();
210 .loc 1 188 3 view .LVU27
211 0002 FFF7FEFF bl HAL_IncTick
212 .LVL0:
189:Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
190:Src/stm32f4xx_it.c ****
191:Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
192:Src/stm32f4xx_it.c **** }
213 .loc 1 192 1 is_stmt 0 view .LVU28
214 0006 08BD pop {r3, pc}
215 .cfi_endproc
216 .LFE142:
218 .text
219 .Letext0:
220 .file 2 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/cctvVj0a.s page 8
ARM GAS /tmp/cctvVj0a.s page 9
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_it.c
/tmp/cctvVj0a.s:20 .text.NMI_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:26 .text.NMI_Handler:0000000000000000 NMI_Handler
/tmp/cctvVj0a.s:44 .text.HardFault_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:50 .text.HardFault_Handler:0000000000000000 HardFault_Handler
/tmp/cctvVj0a.s:67 .text.MemManage_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:73 .text.MemManage_Handler:0000000000000000 MemManage_Handler
/tmp/cctvVj0a.s:90 .text.BusFault_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:96 .text.BusFault_Handler:0000000000000000 BusFault_Handler
/tmp/cctvVj0a.s:113 .text.UsageFault_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:119 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler
/tmp/cctvVj0a.s:136 .text.SVC_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:142 .text.SVC_Handler:0000000000000000 SVC_Handler
/tmp/cctvVj0a.s:155 .text.DebugMon_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:161 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler
/tmp/cctvVj0a.s:174 .text.PendSV_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:180 .text.PendSV_Handler:0000000000000000 PendSV_Handler
/tmp/cctvVj0a.s:193 .text.SysTick_Handler:0000000000000000 $t
/tmp/cctvVj0a.s:199 .text.SysTick_Handler:0000000000000000 SysTick_Handler
UNDEFINED SYMBOLS
HAL_IncTick

589
build/system_stm32f4xx.lst Normal file
View File

@ -0,0 +1,589 @@
ARM GAS /tmp/cckltHc8.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "system_stm32f4xx.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.SystemInit,"ax",%progbits
20 .align 1
21 .global SystemInit
22 .syntax unified
23 .thumb
24 .thumb_func
26 SystemInit:
27 .LFB134:
28 .file 1 "Src/system_stm32f4xx.c"
1:Src/system_stm32f4xx.c **** /**
2:Src/system_stm32f4xx.c **** ******************************************************************************
3:Src/system_stm32f4xx.c **** * @file system_stm32f4xx.c
4:Src/system_stm32f4xx.c **** * @author MCD Application Team
5:Src/system_stm32f4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6:Src/system_stm32f4xx.c **** *
7:Src/system_stm32f4xx.c **** * This file provides two functions and one global variable to be called from
8:Src/system_stm32f4xx.c **** * user application:
9:Src/system_stm32f4xx.c **** * - SystemInit(): This function is called at startup just after reset and
10:Src/system_stm32f4xx.c **** * before branch to main program. This call is made inside
11:Src/system_stm32f4xx.c **** * the "startup_stm32f4xx.s" file.
12:Src/system_stm32f4xx.c **** *
13:Src/system_stm32f4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14:Src/system_stm32f4xx.c **** * by the user application to setup the SysTick
15:Src/system_stm32f4xx.c **** * timer or configure other parameters.
16:Src/system_stm32f4xx.c **** *
17:Src/system_stm32f4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18:Src/system_stm32f4xx.c **** * be called whenever the core clock is changed
19:Src/system_stm32f4xx.c **** * during program execution.
20:Src/system_stm32f4xx.c **** *
21:Src/system_stm32f4xx.c **** *
22:Src/system_stm32f4xx.c **** ******************************************************************************
23:Src/system_stm32f4xx.c **** * @attention
24:Src/system_stm32f4xx.c **** *
25:Src/system_stm32f4xx.c **** * Copyright (c) 2017 STMicroelectronics.
26:Src/system_stm32f4xx.c **** * All rights reserved.
27:Src/system_stm32f4xx.c **** *
28:Src/system_stm32f4xx.c **** * This software is licensed under terms that can be found in the LICENSE file
29:Src/system_stm32f4xx.c **** * in the root directory of this software component.
30:Src/system_stm32f4xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
ARM GAS /tmp/cckltHc8.s page 2
31:Src/system_stm32f4xx.c **** *
32:Src/system_stm32f4xx.c **** ******************************************************************************
33:Src/system_stm32f4xx.c **** */
34:Src/system_stm32f4xx.c ****
35:Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
36:Src/system_stm32f4xx.c **** * @{
37:Src/system_stm32f4xx.c **** */
38:Src/system_stm32f4xx.c ****
39:Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
40:Src/system_stm32f4xx.c **** * @{
41:Src/system_stm32f4xx.c **** */
42:Src/system_stm32f4xx.c ****
43:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
44:Src/system_stm32f4xx.c **** * @{
45:Src/system_stm32f4xx.c **** */
46:Src/system_stm32f4xx.c ****
47:Src/system_stm32f4xx.c ****
48:Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
49:Src/system_stm32f4xx.c ****
50:Src/system_stm32f4xx.c **** #if !defined (HSE_VALUE)
51:Src/system_stm32f4xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
52:Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
53:Src/system_stm32f4xx.c ****
54:Src/system_stm32f4xx.c **** #if !defined (HSI_VALUE)
55:Src/system_stm32f4xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
56:Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
57:Src/system_stm32f4xx.c ****
58:Src/system_stm32f4xx.c **** /**
59:Src/system_stm32f4xx.c **** * @}
60:Src/system_stm32f4xx.c **** */
61:Src/system_stm32f4xx.c ****
62:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
63:Src/system_stm32f4xx.c **** * @{
64:Src/system_stm32f4xx.c **** */
65:Src/system_stm32f4xx.c ****
66:Src/system_stm32f4xx.c **** /**
67:Src/system_stm32f4xx.c **** * @}
68:Src/system_stm32f4xx.c **** */
69:Src/system_stm32f4xx.c ****
70:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
71:Src/system_stm32f4xx.c **** * @{
72:Src/system_stm32f4xx.c **** */
73:Src/system_stm32f4xx.c ****
74:Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
75:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
76:Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
77:Src/system_stm32f4xx.c **** || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
78:Src/system_stm32f4xx.c **** || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
79:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
80:Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
81:Src/system_stm32f4xx.c **** STM32F412Zx || STM32F412Vx */
82:Src/system_stm32f4xx.c ****
83:Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
84:Src/system_stm32f4xx.c **** || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
85:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
86:Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
87:Src/system_stm32f4xx.c **** STM32F479xx */
ARM GAS /tmp/cckltHc8.s page 3
88:Src/system_stm32f4xx.c ****
89:Src/system_stm32f4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
90:Src/system_stm32f4xx.c **** configuration. */
91:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
92:Src/system_stm32f4xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
93:Src/system_stm32f4xx.c **** remap of boot address selected */
94:Src/system_stm32f4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
95:Src/system_stm32f4xx.c ****
96:Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
97:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
98:Src/system_stm32f4xx.c **** in Sram else user remap will be done in Flash. */
99:Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
100:Src/system_stm32f4xx.c **** #if defined(VECT_TAB_SRAM)
101:Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
102:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
103:Src/system_stm32f4xx.c **** #else
104:Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
105:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
106:Src/system_stm32f4xx.c **** #endif /* VECT_TAB_SRAM */
107:Src/system_stm32f4xx.c **** #if !defined(VECT_TAB_OFFSET)
108:Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
109:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
110:Src/system_stm32f4xx.c **** #endif /* VECT_TAB_OFFSET */
111:Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
112:Src/system_stm32f4xx.c **** /******************************************************************************/
113:Src/system_stm32f4xx.c ****
114:Src/system_stm32f4xx.c **** /**
115:Src/system_stm32f4xx.c **** * @}
116:Src/system_stm32f4xx.c **** */
117:Src/system_stm32f4xx.c ****
118:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
119:Src/system_stm32f4xx.c **** * @{
120:Src/system_stm32f4xx.c **** */
121:Src/system_stm32f4xx.c ****
122:Src/system_stm32f4xx.c **** /**
123:Src/system_stm32f4xx.c **** * @}
124:Src/system_stm32f4xx.c **** */
125:Src/system_stm32f4xx.c ****
126:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
127:Src/system_stm32f4xx.c **** * @{
128:Src/system_stm32f4xx.c **** */
129:Src/system_stm32f4xx.c **** /* This variable is updated in three ways:
130:Src/system_stm32f4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
131:Src/system_stm32f4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
132:Src/system_stm32f4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
133:Src/system_stm32f4xx.c **** Note: If you use this function to configure the system clock; then there
134:Src/system_stm32f4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
135:Src/system_stm32f4xx.c **** variable is updated automatically.
136:Src/system_stm32f4xx.c **** */
137:Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
138:Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
139:Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
140:Src/system_stm32f4xx.c **** /**
141:Src/system_stm32f4xx.c **** * @}
142:Src/system_stm32f4xx.c **** */
143:Src/system_stm32f4xx.c ****
144:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
ARM GAS /tmp/cckltHc8.s page 4
145:Src/system_stm32f4xx.c **** * @{
146:Src/system_stm32f4xx.c **** */
147:Src/system_stm32f4xx.c ****
148:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
149:Src/system_stm32f4xx.c **** static void SystemInit_ExtMemCtl(void);
150:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
151:Src/system_stm32f4xx.c ****
152:Src/system_stm32f4xx.c **** /**
153:Src/system_stm32f4xx.c **** * @}
154:Src/system_stm32f4xx.c **** */
155:Src/system_stm32f4xx.c ****
156:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
157:Src/system_stm32f4xx.c **** * @{
158:Src/system_stm32f4xx.c **** */
159:Src/system_stm32f4xx.c ****
160:Src/system_stm32f4xx.c **** /**
161:Src/system_stm32f4xx.c **** * @brief Setup the microcontroller system
162:Src/system_stm32f4xx.c **** * Initialize the FPU setting, vector table location and External memory
163:Src/system_stm32f4xx.c **** * configuration.
164:Src/system_stm32f4xx.c **** * @param None
165:Src/system_stm32f4xx.c **** * @retval None
166:Src/system_stm32f4xx.c **** */
167:Src/system_stm32f4xx.c **** void SystemInit(void)
168:Src/system_stm32f4xx.c **** {
29 .loc 1 168 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
169:Src/system_stm32f4xx.c **** /* FPU settings ------------------------------------------------------------*/
170:Src/system_stm32f4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
171:Src/system_stm32f4xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
34 .loc 1 171 5 view .LVU1
35 .loc 1 171 16 is_stmt 0 view .LVU2
36 0000 034A ldr r2, .L2
37 0002 D2F88830 ldr r3, [r2, #136]
38 0006 43F47003 orr r3, r3, #15728640
39 000a C2F88830 str r3, [r2, #136]
172:Src/system_stm32f4xx.c **** #endif
173:Src/system_stm32f4xx.c ****
174:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
175:Src/system_stm32f4xx.c **** SystemInit_ExtMemCtl();
176:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
177:Src/system_stm32f4xx.c ****
178:Src/system_stm32f4xx.c **** /* Configure the Vector Table location -------------------------------------*/
179:Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
180:Src/system_stm32f4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
181:Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
182:Src/system_stm32f4xx.c **** }
40 .loc 1 182 1 view .LVU3
41 000e 7047 bx lr
42 .L3:
43 .align 2
44 .L2:
45 0010 00ED00E0 .word -536810240
46 .cfi_endproc
47 .LFE134:
ARM GAS /tmp/cckltHc8.s page 5
49 .section .text.SystemCoreClockUpdate,"ax",%progbits
50 .align 1
51 .global SystemCoreClockUpdate
52 .syntax unified
53 .thumb
54 .thumb_func
56 SystemCoreClockUpdate:
57 .LFB135:
183:Src/system_stm32f4xx.c ****
184:Src/system_stm32f4xx.c **** /**
185:Src/system_stm32f4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
186:Src/system_stm32f4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
187:Src/system_stm32f4xx.c **** * be used by the user application to setup the SysTick timer or configure
188:Src/system_stm32f4xx.c **** * other parameters.
189:Src/system_stm32f4xx.c **** *
190:Src/system_stm32f4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
191:Src/system_stm32f4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
192:Src/system_stm32f4xx.c **** * based on this variable will be incorrect.
193:Src/system_stm32f4xx.c **** *
194:Src/system_stm32f4xx.c **** * @note - The system frequency computed by this function is not the real
195:Src/system_stm32f4xx.c **** * frequency in the chip. It is calculated based on the predefined
196:Src/system_stm32f4xx.c **** * constant and the selected clock source:
197:Src/system_stm32f4xx.c **** *
198:Src/system_stm32f4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
199:Src/system_stm32f4xx.c **** *
200:Src/system_stm32f4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
201:Src/system_stm32f4xx.c **** *
202:Src/system_stm32f4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
203:Src/system_stm32f4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
204:Src/system_stm32f4xx.c **** *
205:Src/system_stm32f4xx.c **** * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
206:Src/system_stm32f4xx.c **** * 16 MHz) but the real value may vary depending on the variations
207:Src/system_stm32f4xx.c **** * in voltage and temperature.
208:Src/system_stm32f4xx.c **** *
209:Src/system_stm32f4xx.c **** * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
210:Src/system_stm32f4xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE
211:Src/system_stm32f4xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function
212:Src/system_stm32f4xx.c **** * may have wrong result.
213:Src/system_stm32f4xx.c **** *
214:Src/system_stm32f4xx.c **** * - The result of this function could be not correct when using fractional
215:Src/system_stm32f4xx.c **** * value for HSE crystal.
216:Src/system_stm32f4xx.c **** *
217:Src/system_stm32f4xx.c **** * @param None
218:Src/system_stm32f4xx.c **** * @retval None
219:Src/system_stm32f4xx.c **** */
220:Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
221:Src/system_stm32f4xx.c **** {
58 .loc 1 221 1 is_stmt 1 view -0
59 .cfi_startproc
60 @ args = 0, pretend = 0, frame = 0
61 @ frame_needed = 0, uses_anonymous_args = 0
62 @ link register save eliminated.
222:Src/system_stm32f4xx.c **** uint32_t tmp, pllvco, pllp, pllsource, pllm;
63 .loc 1 222 3 view .LVU5
223:Src/system_stm32f4xx.c ****
224:Src/system_stm32f4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
225:Src/system_stm32f4xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
ARM GAS /tmp/cckltHc8.s page 6
64 .loc 1 225 3 view .LVU6
65 .loc 1 225 12 is_stmt 0 view .LVU7
66 0000 224B ldr r3, .L12
67 0002 9B68 ldr r3, [r3, #8]
68 .loc 1 225 7 view .LVU8
69 0004 03F00C03 and r3, r3, #12
70 .LVL0:
226:Src/system_stm32f4xx.c ****
227:Src/system_stm32f4xx.c **** switch (tmp)
71 .loc 1 227 3 is_stmt 1 view .LVU9
72 0008 042B cmp r3, #4
73 000a 14D0 beq .L5
74 000c 082B cmp r3, #8
75 000e 16D0 beq .L6
76 0010 1BB1 cbz r3, .L11
228:Src/system_stm32f4xx.c **** {
229:Src/system_stm32f4xx.c **** case 0x00: /* HSI used as system clock source */
230:Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
231:Src/system_stm32f4xx.c **** break;
232:Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */
233:Src/system_stm32f4xx.c **** SystemCoreClock = HSE_VALUE;
234:Src/system_stm32f4xx.c **** break;
235:Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
236:Src/system_stm32f4xx.c ****
237:Src/system_stm32f4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
238:Src/system_stm32f4xx.c **** SYSCLK = PLL_VCO / PLL_P
239:Src/system_stm32f4xx.c **** */
240:Src/system_stm32f4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
241:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
242:Src/system_stm32f4xx.c ****
243:Src/system_stm32f4xx.c **** if (pllsource != 0)
244:Src/system_stm32f4xx.c **** {
245:Src/system_stm32f4xx.c **** /* HSE used as PLL clock source */
246:Src/system_stm32f4xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
247:Src/system_stm32f4xx.c **** }
248:Src/system_stm32f4xx.c **** else
249:Src/system_stm32f4xx.c **** {
250:Src/system_stm32f4xx.c **** /* HSI used as PLL clock source */
251:Src/system_stm32f4xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
252:Src/system_stm32f4xx.c **** }
253:Src/system_stm32f4xx.c ****
254:Src/system_stm32f4xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
255:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
256:Src/system_stm32f4xx.c **** break;
257:Src/system_stm32f4xx.c **** default:
258:Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
77 .loc 1 258 7 view .LVU10
78 .loc 1 258 23 is_stmt 0 view .LVU11
79 0012 1F4B ldr r3, .L12+4
80 .LVL1:
81 .loc 1 258 23 view .LVU12
82 0014 1F4A ldr r2, .L12+8
83 0016 1A60 str r2, [r3]
259:Src/system_stm32f4xx.c **** break;
84 .loc 1 259 7 is_stmt 1 view .LVU13
85 0018 02E0 b .L8
86 .LVL2:
ARM GAS /tmp/cckltHc8.s page 7
87 .L11:
230:Src/system_stm32f4xx.c **** break;
88 .loc 1 230 7 view .LVU14
230:Src/system_stm32f4xx.c **** break;
89 .loc 1 230 23 is_stmt 0 view .LVU15
90 001a 1D4B ldr r3, .L12+4
91 .LVL3:
230:Src/system_stm32f4xx.c **** break;
92 .loc 1 230 23 view .LVU16
93 001c 1D4A ldr r2, .L12+8
94 001e 1A60 str r2, [r3]
231:Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */
95 .loc 1 231 7 is_stmt 1 view .LVU17
96 .L8:
260:Src/system_stm32f4xx.c **** }
261:Src/system_stm32f4xx.c **** /* Compute HCLK frequency --------------------------------------------------*/
262:Src/system_stm32f4xx.c **** /* Get HCLK prescaler */
263:Src/system_stm32f4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
97 .loc 1 263 3 view .LVU18
98 .loc 1 263 28 is_stmt 0 view .LVU19
99 0020 1A4B ldr r3, .L12
100 0022 9B68 ldr r3, [r3, #8]
101 .loc 1 263 52 view .LVU20
102 0024 C3F30313 ubfx r3, r3, #4, #4
103 .loc 1 263 22 view .LVU21
104 0028 1B4A ldr r2, .L12+12
105 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
106 .LVL4:
264:Src/system_stm32f4xx.c **** /* HCLK frequency */
265:Src/system_stm32f4xx.c **** SystemCoreClock >>= tmp;
107 .loc 1 265 3 is_stmt 1 view .LVU22
108 .loc 1 265 19 is_stmt 0 view .LVU23
109 002c 184A ldr r2, .L12+4
110 002e 1368 ldr r3, [r2]
111 0030 CB40 lsrs r3, r3, r1
112 0032 1360 str r3, [r2]
266:Src/system_stm32f4xx.c **** }
113 .loc 1 266 1 view .LVU24
114 0034 7047 bx lr
115 .LVL5:
116 .L5:
233:Src/system_stm32f4xx.c **** break;
117 .loc 1 233 7 is_stmt 1 view .LVU25
233:Src/system_stm32f4xx.c **** break;
118 .loc 1 233 23 is_stmt 0 view .LVU26
119 0036 164B ldr r3, .L12+4
120 .LVL6:
233:Src/system_stm32f4xx.c **** break;
121 .loc 1 233 23 view .LVU27
122 0038 184A ldr r2, .L12+16
123 003a 1A60 str r2, [r3]
234:Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
124 .loc 1 234 7 is_stmt 1 view .LVU28
125 003c F0E7 b .L8
126 .LVL7:
127 .L6:
240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
ARM GAS /tmp/cckltHc8.s page 8
128 .loc 1 240 7 view .LVU29
240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
129 .loc 1 240 23 is_stmt 0 view .LVU30
130 003e 134B ldr r3, .L12
131 .LVL8:
240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
132 .loc 1 240 23 view .LVU31
133 0040 5968 ldr r1, [r3, #4]
134 .LVL9:
241:Src/system_stm32f4xx.c ****
135 .loc 1 241 7 is_stmt 1 view .LVU32
241:Src/system_stm32f4xx.c ****
136 .loc 1 241 17 is_stmt 0 view .LVU33
137 0042 5A68 ldr r2, [r3, #4]
241:Src/system_stm32f4xx.c ****
138 .loc 1 241 12 view .LVU34
139 0044 02F03F02 and r2, r2, #63
140 .LVL10:
243:Src/system_stm32f4xx.c **** {
141 .loc 1 243 7 is_stmt 1 view .LVU35
243:Src/system_stm32f4xx.c **** {
142 .loc 1 243 10 is_stmt 0 view .LVU36
143 0048 11F4800F tst r1, #4194304
144 004c 13D0 beq .L9
246:Src/system_stm32f4xx.c **** }
145 .loc 1 246 9 is_stmt 1 view .LVU37
246:Src/system_stm32f4xx.c **** }
146 .loc 1 246 29 is_stmt 0 view .LVU38
147 004e 134B ldr r3, .L12+16
148 0050 B3FBF2F3 udiv r3, r3, r2
246:Src/system_stm32f4xx.c **** }
149 .loc 1 246 44 view .LVU39
150 0054 0D4A ldr r2, .L12
151 .LVL11:
246:Src/system_stm32f4xx.c **** }
152 .loc 1 246 44 view .LVU40
153 0056 5268 ldr r2, [r2, #4]
246:Src/system_stm32f4xx.c **** }
154 .loc 1 246 74 view .LVU41
155 0058 C2F38812 ubfx r2, r2, #6, #9
246:Src/system_stm32f4xx.c **** }
156 .loc 1 246 16 view .LVU42
157 005c 02FB03F3 mul r3, r2, r3
158 .LVL12:
159 .L10:
254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
160 .loc 1 254 7 is_stmt 1 view .LVU43
254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
161 .loc 1 254 20 is_stmt 0 view .LVU44
162 0060 0A4A ldr r2, .L12
163 0062 5268 ldr r2, [r2, #4]
254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
164 .loc 1 254 50 view .LVU45
165 0064 C2F30142 ubfx r2, r2, #16, #2
254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
166 .loc 1 254 56 view .LVU46
167 0068 0132 adds r2, r2, #1
ARM GAS /tmp/cckltHc8.s page 9
254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
168 .loc 1 254 12 view .LVU47
169 006a 5200 lsls r2, r2, #1
170 .LVL13:
255:Src/system_stm32f4xx.c **** break;
171 .loc 1 255 7 is_stmt 1 view .LVU48
255:Src/system_stm32f4xx.c **** break;
172 .loc 1 255 31 is_stmt 0 view .LVU49
173 006c B3FBF2F3 udiv r3, r3, r2
174 .LVL14:
255:Src/system_stm32f4xx.c **** break;
175 .loc 1 255 23 view .LVU50
176 0070 074A ldr r2, .L12+4
177 .LVL15:
255:Src/system_stm32f4xx.c **** break;
178 .loc 1 255 23 view .LVU51
179 0072 1360 str r3, [r2]
256:Src/system_stm32f4xx.c **** default:
180 .loc 1 256 7 is_stmt 1 view .LVU52
181 0074 D4E7 b .L8
182 .LVL16:
183 .L9:
251:Src/system_stm32f4xx.c **** }
184 .loc 1 251 9 view .LVU53
251:Src/system_stm32f4xx.c **** }
185 .loc 1 251 29 is_stmt 0 view .LVU54
186 0076 074B ldr r3, .L12+8
187 0078 B3FBF2F3 udiv r3, r3, r2
251:Src/system_stm32f4xx.c **** }
188 .loc 1 251 44 view .LVU55
189 007c 034A ldr r2, .L12
190 .LVL17:
251:Src/system_stm32f4xx.c **** }
191 .loc 1 251 44 view .LVU56
192 007e 5268 ldr r2, [r2, #4]
251:Src/system_stm32f4xx.c **** }
193 .loc 1 251 74 view .LVU57
194 0080 C2F38812 ubfx r2, r2, #6, #9
251:Src/system_stm32f4xx.c **** }
195 .loc 1 251 16 view .LVU58
196 0084 02FB03F3 mul r3, r2, r3
197 .LVL18:
251:Src/system_stm32f4xx.c **** }
198 .loc 1 251 16 view .LVU59
199 0088 EAE7 b .L10
200 .L13:
201 008a 00BF .align 2
202 .L12:
203 008c 00380240 .word 1073887232
204 0090 00000000 .word .LANCHOR0
205 0094 0024F400 .word 16000000
206 0098 00000000 .word .LANCHOR1
207 009c 00127A00 .word 8000000
208 .cfi_endproc
209 .LFE135:
211 .global APBPrescTable
212 .global AHBPrescTable
ARM GAS /tmp/cckltHc8.s page 10
213 .global SystemCoreClock
214 .section .data.SystemCoreClock,"aw"
215 .align 2
216 .set .LANCHOR0,. + 0
219 SystemCoreClock:
220 0000 0024F400 .word 16000000
221 .section .rodata.AHBPrescTable,"a"
222 .align 2
223 .set .LANCHOR1,. + 0
226 AHBPrescTable:
227 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
227 00000000
227 01020304
227 06
228 000d 070809 .ascii "\007\010\011"
229 .section .rodata.APBPrescTable,"a"
230 .align 2
233 APBPrescTable:
234 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
234 01020304
235 .text
236 .Letext0:
237 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
238 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
239 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
240 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
241 .file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
ARM GAS /tmp/cckltHc8.s page 11
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32f4xx.c
/tmp/cckltHc8.s:20 .text.SystemInit:0000000000000000 $t
/tmp/cckltHc8.s:26 .text.SystemInit:0000000000000000 SystemInit
/tmp/cckltHc8.s:45 .text.SystemInit:0000000000000010 $d
/tmp/cckltHc8.s:50 .text.SystemCoreClockUpdate:0000000000000000 $t
/tmp/cckltHc8.s:56 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
/tmp/cckltHc8.s:203 .text.SystemCoreClockUpdate:000000000000008c $d
/tmp/cckltHc8.s:233 .rodata.APBPrescTable:0000000000000000 APBPrescTable
/tmp/cckltHc8.s:226 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
/tmp/cckltHc8.s:219 .data.SystemCoreClock:0000000000000000 SystemCoreClock
/tmp/cckltHc8.s:215 .data.SystemCoreClock:0000000000000000 $d
/tmp/cckltHc8.s:222 .rodata.AHBPrescTable:0000000000000000 $d
/tmp/cckltHc8.s:230 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS

BIN
build/test.bin Normal file
View File

Binary file not shown.

324
build/tim.lst Normal file
View File

@ -0,0 +1,324 @@
ARM GAS /tmp/cctYDink.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "tim.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_TIM13_Init,"ax",%progbits
20 .align 1
21 .global MX_TIM13_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_TIM13_Init:
27 .LFB134:
28 .file 1 "Src/tim.c"
1:Src/tim.c **** /* USER CODE BEGIN Header */
2:Src/tim.c **** /**
3:Src/tim.c **** ******************************************************************************
4:Src/tim.c **** * @file tim.c
5:Src/tim.c **** * @brief This file provides code for the configuration
6:Src/tim.c **** * of the TIM instances.
7:Src/tim.c **** ******************************************************************************
8:Src/tim.c **** * @attention
9:Src/tim.c **** *
10:Src/tim.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/tim.c **** * All rights reserved.
12:Src/tim.c **** *
13:Src/tim.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/tim.c **** * in the root directory of this software component.
15:Src/tim.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/tim.c **** *
17:Src/tim.c **** ******************************************************************************
18:Src/tim.c **** */
19:Src/tim.c **** /* USER CODE END Header */
20:Src/tim.c **** /* Includes ------------------------------------------------------------------*/
21:Src/tim.c **** #include "tim.h"
22:Src/tim.c ****
23:Src/tim.c **** /* USER CODE BEGIN 0 */
24:Src/tim.c ****
25:Src/tim.c **** /* USER CODE END 0 */
26:Src/tim.c ****
27:Src/tim.c **** TIM_HandleTypeDef htim13;
28:Src/tim.c ****
29:Src/tim.c **** /* TIM13 init function */
30:Src/tim.c **** void MX_TIM13_Init(void)
ARM GAS /tmp/cctYDink.s page 2
31:Src/tim.c **** {
29 .loc 1 31 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 08B5 push {r3, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
32:Src/tim.c ****
33:Src/tim.c **** /* USER CODE BEGIN TIM13_Init 0 */
34:Src/tim.c ****
35:Src/tim.c **** /* USER CODE END TIM13_Init 0 */
36:Src/tim.c ****
37:Src/tim.c **** /* USER CODE BEGIN TIM13_Init 1 */
38:Src/tim.c ****
39:Src/tim.c **** /* USER CODE END TIM13_Init 1 */
40:Src/tim.c **** htim13.Instance = TIM13;
38 .loc 1 40 3 view .LVU1
39 .loc 1 40 19 is_stmt 0 view .LVU2
40 0002 0948 ldr r0, .L5
41 0004 094B ldr r3, .L5+4
42 0006 0360 str r3, [r0]
41:Src/tim.c **** htim13.Init.Prescaler = 0;
43 .loc 1 41 3 is_stmt 1 view .LVU3
44 .loc 1 41 25 is_stmt 0 view .LVU4
45 0008 0023 movs r3, #0
46 000a 4360 str r3, [r0, #4]
42:Src/tim.c **** htim13.Init.CounterMode = TIM_COUNTERMODE_UP;
47 .loc 1 42 3 is_stmt 1 view .LVU5
48 .loc 1 42 27 is_stmt 0 view .LVU6
49 000c 8360 str r3, [r0, #8]
43:Src/tim.c **** htim13.Init.Period = 65535;
50 .loc 1 43 3 is_stmt 1 view .LVU7
51 .loc 1 43 22 is_stmt 0 view .LVU8
52 000e 4FF6FF72 movw r2, #65535
53 0012 C260 str r2, [r0, #12]
44:Src/tim.c **** htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
54 .loc 1 44 3 is_stmt 1 view .LVU9
55 .loc 1 44 29 is_stmt 0 view .LVU10
56 0014 0361 str r3, [r0, #16]
45:Src/tim.c **** htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
57 .loc 1 45 3 is_stmt 1 view .LVU11
58 .loc 1 45 33 is_stmt 0 view .LVU12
59 0016 8361 str r3, [r0, #24]
46:Src/tim.c **** if (HAL_TIM_Base_Init(&htim13) != HAL_OK)
60 .loc 1 46 3 is_stmt 1 view .LVU13
61 .loc 1 46 7 is_stmt 0 view .LVU14
62 0018 FFF7FEFF bl HAL_TIM_Base_Init
63 .LVL0:
64 .loc 1 46 6 view .LVU15
65 001c 00B9 cbnz r0, .L4
66 .L1:
47:Src/tim.c **** {
48:Src/tim.c **** Error_Handler();
49:Src/tim.c **** }
ARM GAS /tmp/cctYDink.s page 3
50:Src/tim.c **** /* USER CODE BEGIN TIM13_Init 2 */
51:Src/tim.c ****
52:Src/tim.c **** /* USER CODE END TIM13_Init 2 */
53:Src/tim.c ****
54:Src/tim.c **** }
67 .loc 1 54 1 view .LVU16
68 001e 08BD pop {r3, pc}
69 .L4:
48:Src/tim.c **** }
70 .loc 1 48 5 is_stmt 1 view .LVU17
71 0020 FFF7FEFF bl Error_Handler
72 .LVL1:
73 .loc 1 54 1 is_stmt 0 view .LVU18
74 0024 FBE7 b .L1
75 .L6:
76 0026 00BF .align 2
77 .L5:
78 0028 00000000 .word .LANCHOR0
79 002c 001C0040 .word 1073748992
80 .cfi_endproc
81 .LFE134:
83 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits
84 .align 1
85 .global HAL_TIM_Base_MspInit
86 .syntax unified
87 .thumb
88 .thumb_func
90 HAL_TIM_Base_MspInit:
91 .LVL2:
92 .LFB135:
55:Src/tim.c ****
56:Src/tim.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
57:Src/tim.c **** {
93 .loc 1 57 1 is_stmt 1 view -0
94 .cfi_startproc
95 @ args = 0, pretend = 0, frame = 8
96 @ frame_needed = 0, uses_anonymous_args = 0
97 @ link register save eliminated.
58:Src/tim.c ****
59:Src/tim.c **** if(tim_baseHandle->Instance==TIM13)
98 .loc 1 59 3 view .LVU20
99 .loc 1 59 20 is_stmt 0 view .LVU21
100 0000 0268 ldr r2, [r0]
101 .loc 1 59 5 view .LVU22
102 0002 094B ldr r3, .L14
103 0004 9A42 cmp r2, r3
104 0006 00D0 beq .L13
105 0008 7047 bx lr
106 .L13:
57:Src/tim.c ****
107 .loc 1 57 1 view .LVU23
108 000a 82B0 sub sp, sp, #8
109 .LCFI1:
110 .cfi_def_cfa_offset 8
60:Src/tim.c **** {
61:Src/tim.c **** /* USER CODE BEGIN TIM13_MspInit 0 */
62:Src/tim.c ****
ARM GAS /tmp/cctYDink.s page 4
63:Src/tim.c **** /* USER CODE END TIM13_MspInit 0 */
64:Src/tim.c **** /* TIM13 clock enable */
65:Src/tim.c **** __HAL_RCC_TIM13_CLK_ENABLE();
111 .loc 1 65 5 is_stmt 1 view .LVU24
112 .LBB2:
113 .loc 1 65 5 view .LVU25
114 000c 0023 movs r3, #0
115 000e 0193 str r3, [sp, #4]
116 .loc 1 65 5 view .LVU26
117 0010 064B ldr r3, .L14+4
118 0012 1A6C ldr r2, [r3, #64]
119 0014 42F08002 orr r2, r2, #128
120 0018 1A64 str r2, [r3, #64]
121 .loc 1 65 5 view .LVU27
122 001a 1B6C ldr r3, [r3, #64]
123 001c 03F08003 and r3, r3, #128
124 0020 0193 str r3, [sp, #4]
125 .loc 1 65 5 view .LVU28
126 0022 019B ldr r3, [sp, #4]
127 .LBE2:
128 .loc 1 65 5 view .LVU29
66:Src/tim.c **** /* USER CODE BEGIN TIM13_MspInit 1 */
67:Src/tim.c ****
68:Src/tim.c **** /* USER CODE END TIM13_MspInit 1 */
69:Src/tim.c **** }
70:Src/tim.c **** }
129 .loc 1 70 1 is_stmt 0 view .LVU30
130 0024 02B0 add sp, sp, #8
131 .LCFI2:
132 .cfi_def_cfa_offset 0
133 @ sp needed
134 0026 7047 bx lr
135 .L15:
136 .align 2
137 .L14:
138 0028 001C0040 .word 1073748992
139 002c 00380240 .word 1073887232
140 .cfi_endproc
141 .LFE135:
143 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits
144 .align 1
145 .global HAL_TIM_Base_MspDeInit
146 .syntax unified
147 .thumb
148 .thumb_func
150 HAL_TIM_Base_MspDeInit:
151 .LVL3:
152 .LFB136:
71:Src/tim.c ****
72:Src/tim.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
73:Src/tim.c **** {
153 .loc 1 73 1 is_stmt 1 view -0
154 .cfi_startproc
155 @ args = 0, pretend = 0, frame = 0
156 @ frame_needed = 0, uses_anonymous_args = 0
157 @ link register save eliminated.
74:Src/tim.c ****
ARM GAS /tmp/cctYDink.s page 5
75:Src/tim.c **** if(tim_baseHandle->Instance==TIM13)
158 .loc 1 75 3 view .LVU32
159 .loc 1 75 20 is_stmt 0 view .LVU33
160 0000 0268 ldr r2, [r0]
161 .loc 1 75 5 view .LVU34
162 0002 054B ldr r3, .L19
163 0004 9A42 cmp r2, r3
164 0006 00D0 beq .L18
165 .L16:
76:Src/tim.c **** {
77:Src/tim.c **** /* USER CODE BEGIN TIM13_MspDeInit 0 */
78:Src/tim.c ****
79:Src/tim.c **** /* USER CODE END TIM13_MspDeInit 0 */
80:Src/tim.c **** /* Peripheral clock disable */
81:Src/tim.c **** __HAL_RCC_TIM13_CLK_DISABLE();
82:Src/tim.c **** /* USER CODE BEGIN TIM13_MspDeInit 1 */
83:Src/tim.c ****
84:Src/tim.c **** /* USER CODE END TIM13_MspDeInit 1 */
85:Src/tim.c **** }
86:Src/tim.c **** }
166 .loc 1 86 1 view .LVU35
167 0008 7047 bx lr
168 .L18:
81:Src/tim.c **** /* USER CODE BEGIN TIM13_MspDeInit 1 */
169 .loc 1 81 5 is_stmt 1 view .LVU36
170 000a 044A ldr r2, .L19+4
171 000c 136C ldr r3, [r2, #64]
172 000e 23F08003 bic r3, r3, #128
173 0012 1364 str r3, [r2, #64]
174 .loc 1 86 1 is_stmt 0 view .LVU37
175 0014 F8E7 b .L16
176 .L20:
177 0016 00BF .align 2
178 .L19:
179 0018 001C0040 .word 1073748992
180 001c 00380240 .word 1073887232
181 .cfi_endproc
182 .LFE136:
184 .global htim13
185 .section .bss.htim13,"aw",%nobits
186 .align 2
187 .set .LANCHOR0,. + 0
190 htim13:
191 0000 00000000 .space 72
191 00000000
191 00000000
191 00000000
191 00000000
192 .text
193 .Letext0:
194 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
195 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
196 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
197 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
198 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
199 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h"
200 .file 8 "Inc/main.h"
ARM GAS /tmp/cctYDink.s page 6
201 .file 9 "Inc/tim.h"
ARM GAS /tmp/cctYDink.s page 7
DEFINED SYMBOLS
*ABS*:0000000000000000 tim.c
/tmp/cctYDink.s:20 .text.MX_TIM13_Init:0000000000000000 $t
/tmp/cctYDink.s:26 .text.MX_TIM13_Init:0000000000000000 MX_TIM13_Init
/tmp/cctYDink.s:78 .text.MX_TIM13_Init:0000000000000028 $d
/tmp/cctYDink.s:84 .text.HAL_TIM_Base_MspInit:0000000000000000 $t
/tmp/cctYDink.s:90 .text.HAL_TIM_Base_MspInit:0000000000000000 HAL_TIM_Base_MspInit
/tmp/cctYDink.s:138 .text.HAL_TIM_Base_MspInit:0000000000000028 $d
/tmp/cctYDink.s:144 .text.HAL_TIM_Base_MspDeInit:0000000000000000 $t
/tmp/cctYDink.s:150 .text.HAL_TIM_Base_MspDeInit:0000000000000000 HAL_TIM_Base_MspDeInit
/tmp/cctYDink.s:179 .text.HAL_TIM_Base_MspDeInit:0000000000000018 $d
/tmp/cctYDink.s:190 .bss.htim13:0000000000000000 htim13
/tmp/cctYDink.s:186 .bss.htim13:0000000000000000 $d
UNDEFINED SYMBOLS
HAL_TIM_Base_Init
Error_Handler

461
build/usart.lst Normal file
View File

@ -0,0 +1,461 @@
ARM GAS /tmp/ccGGuUQz.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "usart.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_USART1_UART_Init,"ax",%progbits
20 .align 1
21 .global MX_USART1_UART_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_USART1_UART_Init:
27 .LFB134:
28 .file 1 "Src/usart.c"
1:Src/usart.c **** /* USER CODE BEGIN Header */
2:Src/usart.c **** /**
3:Src/usart.c **** ******************************************************************************
4:Src/usart.c **** * @file usart.c
5:Src/usart.c **** * @brief This file provides code for the configuration
6:Src/usart.c **** * of the USART instances.
7:Src/usart.c **** ******************************************************************************
8:Src/usart.c **** * @attention
9:Src/usart.c **** *
10:Src/usart.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/usart.c **** * All rights reserved.
12:Src/usart.c **** *
13:Src/usart.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/usart.c **** * in the root directory of this software component.
15:Src/usart.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/usart.c **** *
17:Src/usart.c **** ******************************************************************************
18:Src/usart.c **** */
19:Src/usart.c **** /* USER CODE END Header */
20:Src/usart.c **** /* Includes ------------------------------------------------------------------*/
21:Src/usart.c **** #include "usart.h"
22:Src/usart.c ****
23:Src/usart.c **** /* USER CODE BEGIN 0 */
24:Src/usart.c ****
25:Src/usart.c **** /* USER CODE END 0 */
26:Src/usart.c ****
27:Src/usart.c **** UART_HandleTypeDef huart1;
28:Src/usart.c ****
29:Src/usart.c **** /* USART1 init function */
30:Src/usart.c ****
ARM GAS /tmp/ccGGuUQz.s page 2
31:Src/usart.c **** void MX_USART1_UART_Init(void)
32:Src/usart.c **** {
29 .loc 1 32 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 08B5 push {r3, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
33:Src/usart.c ****
34:Src/usart.c **** /* USER CODE BEGIN USART1_Init 0 */
35:Src/usart.c ****
36:Src/usart.c **** /* USER CODE END USART1_Init 0 */
37:Src/usart.c ****
38:Src/usart.c **** /* USER CODE BEGIN USART1_Init 1 */
39:Src/usart.c ****
40:Src/usart.c **** /* USER CODE END USART1_Init 1 */
41:Src/usart.c **** huart1.Instance = USART1;
38 .loc 1 41 3 view .LVU1
39 .loc 1 41 19 is_stmt 0 view .LVU2
40 0002 0A48 ldr r0, .L5
41 0004 0A4B ldr r3, .L5+4
42 0006 0360 str r3, [r0]
42:Src/usart.c **** huart1.Init.BaudRate = 115200;
43 .loc 1 42 3 is_stmt 1 view .LVU3
44 .loc 1 42 24 is_stmt 0 view .LVU4
45 0008 4FF4E133 mov r3, #115200
46 000c 4360 str r3, [r0, #4]
43:Src/usart.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
47 .loc 1 43 3 is_stmt 1 view .LVU5
48 .loc 1 43 26 is_stmt 0 view .LVU6
49 000e 0023 movs r3, #0
50 0010 8360 str r3, [r0, #8]
44:Src/usart.c **** huart1.Init.StopBits = UART_STOPBITS_1;
51 .loc 1 44 3 is_stmt 1 view .LVU7
52 .loc 1 44 24 is_stmt 0 view .LVU8
53 0012 C360 str r3, [r0, #12]
45:Src/usart.c **** huart1.Init.Parity = UART_PARITY_NONE;
54 .loc 1 45 3 is_stmt 1 view .LVU9
55 .loc 1 45 22 is_stmt 0 view .LVU10
56 0014 0361 str r3, [r0, #16]
46:Src/usart.c **** huart1.Init.Mode = UART_MODE_TX_RX;
57 .loc 1 46 3 is_stmt 1 view .LVU11
58 .loc 1 46 20 is_stmt 0 view .LVU12
59 0016 0C22 movs r2, #12
60 0018 4261 str r2, [r0, #20]
47:Src/usart.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
61 .loc 1 47 3 is_stmt 1 view .LVU13
62 .loc 1 47 25 is_stmt 0 view .LVU14
63 001a 8361 str r3, [r0, #24]
48:Src/usart.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16;
64 .loc 1 48 3 is_stmt 1 view .LVU15
65 .loc 1 48 28 is_stmt 0 view .LVU16
66 001c C361 str r3, [r0, #28]
49:Src/usart.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
ARM GAS /tmp/ccGGuUQz.s page 3
67 .loc 1 49 3 is_stmt 1 view .LVU17
68 .loc 1 49 7 is_stmt 0 view .LVU18
69 001e FFF7FEFF bl HAL_UART_Init
70 .LVL0:
71 .loc 1 49 6 view .LVU19
72 0022 00B9 cbnz r0, .L4
73 .L1:
50:Src/usart.c **** {
51:Src/usart.c **** Error_Handler();
52:Src/usart.c **** }
53:Src/usart.c **** /* USER CODE BEGIN USART1_Init 2 */
54:Src/usart.c ****
55:Src/usart.c **** /* USER CODE END USART1_Init 2 */
56:Src/usart.c ****
57:Src/usart.c **** }
74 .loc 1 57 1 view .LVU20
75 0024 08BD pop {r3, pc}
76 .L4:
51:Src/usart.c **** }
77 .loc 1 51 5 is_stmt 1 view .LVU21
78 0026 FFF7FEFF bl Error_Handler
79 .LVL1:
80 .loc 1 57 1 is_stmt 0 view .LVU22
81 002a FBE7 b .L1
82 .L6:
83 .align 2
84 .L5:
85 002c 00000000 .word .LANCHOR0
86 0030 00100140 .word 1073811456
87 .cfi_endproc
88 .LFE134:
90 .section .text.HAL_UART_MspInit,"ax",%progbits
91 .align 1
92 .global HAL_UART_MspInit
93 .syntax unified
94 .thumb
95 .thumb_func
97 HAL_UART_MspInit:
98 .LVL2:
99 .LFB135:
58:Src/usart.c ****
59:Src/usart.c **** void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
60:Src/usart.c **** {
100 .loc 1 60 1 is_stmt 1 view -0
101 .cfi_startproc
102 @ args = 0, pretend = 0, frame = 32
103 @ frame_needed = 0, uses_anonymous_args = 0
104 .loc 1 60 1 is_stmt 0 view .LVU24
105 0000 00B5 push {lr}
106 .LCFI1:
107 .cfi_def_cfa_offset 4
108 .cfi_offset 14, -4
109 0002 89B0 sub sp, sp, #36
110 .LCFI2:
111 .cfi_def_cfa_offset 40
61:Src/usart.c ****
62:Src/usart.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
ARM GAS /tmp/ccGGuUQz.s page 4
112 .loc 1 62 3 is_stmt 1 view .LVU25
113 .loc 1 62 20 is_stmt 0 view .LVU26
114 0004 0023 movs r3, #0
115 0006 0393 str r3, [sp, #12]
116 0008 0493 str r3, [sp, #16]
117 000a 0593 str r3, [sp, #20]
118 000c 0693 str r3, [sp, #24]
119 000e 0793 str r3, [sp, #28]
63:Src/usart.c **** if(uartHandle->Instance==USART1)
120 .loc 1 63 3 is_stmt 1 view .LVU27
121 .loc 1 63 16 is_stmt 0 view .LVU28
122 0010 0268 ldr r2, [r0]
123 .loc 1 63 5 view .LVU29
124 0012 03F18043 add r3, r3, #1073741824
125 0016 03F58833 add r3, r3, #69632
126 001a 9A42 cmp r2, r3
127 001c 02D0 beq .L10
128 .LVL3:
129 .L7:
64:Src/usart.c **** {
65:Src/usart.c **** /* USER CODE BEGIN USART1_MspInit 0 */
66:Src/usart.c ****
67:Src/usart.c **** /* USER CODE END USART1_MspInit 0 */
68:Src/usart.c **** /* USART1 clock enable */
69:Src/usart.c **** __HAL_RCC_USART1_CLK_ENABLE();
70:Src/usart.c ****
71:Src/usart.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
72:Src/usart.c **** /**USART1 GPIO Configuration
73:Src/usart.c **** PA9 ------> USART1_TX
74:Src/usart.c **** PA10 ------> USART1_RX
75:Src/usart.c **** */
76:Src/usart.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
77:Src/usart.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
78:Src/usart.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
79:Src/usart.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80:Src/usart.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
81:Src/usart.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
82:Src/usart.c ****
83:Src/usart.c **** /* USER CODE BEGIN USART1_MspInit 1 */
84:Src/usart.c ****
85:Src/usart.c **** /* USER CODE END USART1_MspInit 1 */
86:Src/usart.c **** }
87:Src/usart.c **** }
130 .loc 1 87 1 view .LVU30
131 001e 09B0 add sp, sp, #36
132 .LCFI3:
133 .cfi_remember_state
134 .cfi_def_cfa_offset 4
135 @ sp needed
136 0020 5DF804FB ldr pc, [sp], #4
137 .LVL4:
138 .L10:
139 .LCFI4:
140 .cfi_restore_state
69:Src/usart.c ****
141 .loc 1 69 5 is_stmt 1 view .LVU31
142 .LBB2:
ARM GAS /tmp/ccGGuUQz.s page 5
69:Src/usart.c ****
143 .loc 1 69 5 view .LVU32
144 0024 0021 movs r1, #0
145 0026 0191 str r1, [sp, #4]
69:Src/usart.c ****
146 .loc 1 69 5 view .LVU33
147 0028 03F59433 add r3, r3, #75776
148 002c 5A6C ldr r2, [r3, #68]
149 002e 42F01002 orr r2, r2, #16
150 0032 5A64 str r2, [r3, #68]
69:Src/usart.c ****
151 .loc 1 69 5 view .LVU34
152 0034 5A6C ldr r2, [r3, #68]
153 0036 02F01002 and r2, r2, #16
154 003a 0192 str r2, [sp, #4]
69:Src/usart.c ****
155 .loc 1 69 5 view .LVU35
156 003c 019A ldr r2, [sp, #4]
157 .LBE2:
69:Src/usart.c ****
158 .loc 1 69 5 view .LVU36
71:Src/usart.c **** /**USART1 GPIO Configuration
159 .loc 1 71 5 view .LVU37
160 .LBB3:
71:Src/usart.c **** /**USART1 GPIO Configuration
161 .loc 1 71 5 view .LVU38
162 003e 0291 str r1, [sp, #8]
71:Src/usart.c **** /**USART1 GPIO Configuration
163 .loc 1 71 5 view .LVU39
164 0040 1A6B ldr r2, [r3, #48]
165 0042 42F00102 orr r2, r2, #1
166 0046 1A63 str r2, [r3, #48]
71:Src/usart.c **** /**USART1 GPIO Configuration
167 .loc 1 71 5 view .LVU40
168 0048 1B6B ldr r3, [r3, #48]
169 004a 03F00103 and r3, r3, #1
170 004e 0293 str r3, [sp, #8]
71:Src/usart.c **** /**USART1 GPIO Configuration
171 .loc 1 71 5 view .LVU41
172 0050 029B ldr r3, [sp, #8]
173 .LBE3:
71:Src/usart.c **** /**USART1 GPIO Configuration
174 .loc 1 71 5 view .LVU42
76:Src/usart.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
175 .loc 1 76 5 view .LVU43
76:Src/usart.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
176 .loc 1 76 25 is_stmt 0 view .LVU44
177 0052 4FF4C063 mov r3, #1536
178 0056 0393 str r3, [sp, #12]
77:Src/usart.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
179 .loc 1 77 5 is_stmt 1 view .LVU45
77:Src/usart.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
180 .loc 1 77 26 is_stmt 0 view .LVU46
181 0058 0223 movs r3, #2
182 005a 0493 str r3, [sp, #16]
78:Src/usart.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
183 .loc 1 78 5 is_stmt 1 view .LVU47
ARM GAS /tmp/ccGGuUQz.s page 6
79:Src/usart.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
184 .loc 1 79 5 view .LVU48
79:Src/usart.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
185 .loc 1 79 27 is_stmt 0 view .LVU49
186 005c 0323 movs r3, #3
187 005e 0693 str r3, [sp, #24]
80:Src/usart.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
188 .loc 1 80 5 is_stmt 1 view .LVU50
80:Src/usart.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
189 .loc 1 80 31 is_stmt 0 view .LVU51
190 0060 0723 movs r3, #7
191 0062 0793 str r3, [sp, #28]
81:Src/usart.c ****
192 .loc 1 81 5 is_stmt 1 view .LVU52
193 0064 03A9 add r1, sp, #12
194 0066 0248 ldr r0, .L11
195 .LVL5:
81:Src/usart.c ****
196 .loc 1 81 5 is_stmt 0 view .LVU53
197 0068 FFF7FEFF bl HAL_GPIO_Init
198 .LVL6:
199 .loc 1 87 1 view .LVU54
200 006c D7E7 b .L7
201 .L12:
202 006e 00BF .align 2
203 .L11:
204 0070 00000240 .word 1073872896
205 .cfi_endproc
206 .LFE135:
208 .section .text.HAL_UART_MspDeInit,"ax",%progbits
209 .align 1
210 .global HAL_UART_MspDeInit
211 .syntax unified
212 .thumb
213 .thumb_func
215 HAL_UART_MspDeInit:
216 .LVL7:
217 .LFB136:
88:Src/usart.c ****
89:Src/usart.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
90:Src/usart.c **** {
218 .loc 1 90 1 is_stmt 1 view -0
219 .cfi_startproc
220 @ args = 0, pretend = 0, frame = 0
221 @ frame_needed = 0, uses_anonymous_args = 0
222 .loc 1 90 1 is_stmt 0 view .LVU56
223 0000 08B5 push {r3, lr}
224 .LCFI5:
225 .cfi_def_cfa_offset 8
226 .cfi_offset 3, -8
227 .cfi_offset 14, -4
91:Src/usart.c ****
92:Src/usart.c **** if(uartHandle->Instance==USART1)
228 .loc 1 92 3 is_stmt 1 view .LVU57
229 .loc 1 92 16 is_stmt 0 view .LVU58
230 0002 0268 ldr r2, [r0]
231 .loc 1 92 5 view .LVU59
ARM GAS /tmp/ccGGuUQz.s page 7
232 0004 074B ldr r3, .L17
233 0006 9A42 cmp r2, r3
234 0008 00D0 beq .L16
235 .LVL8:
236 .L13:
93:Src/usart.c **** {
94:Src/usart.c **** /* USER CODE BEGIN USART1_MspDeInit 0 */
95:Src/usart.c ****
96:Src/usart.c **** /* USER CODE END USART1_MspDeInit 0 */
97:Src/usart.c **** /* Peripheral clock disable */
98:Src/usart.c **** __HAL_RCC_USART1_CLK_DISABLE();
99:Src/usart.c ****
100:Src/usart.c **** /**USART1 GPIO Configuration
101:Src/usart.c **** PA9 ------> USART1_TX
102:Src/usart.c **** PA10 ------> USART1_RX
103:Src/usart.c **** */
104:Src/usart.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
105:Src/usart.c ****
106:Src/usart.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */
107:Src/usart.c ****
108:Src/usart.c **** /* USER CODE END USART1_MspDeInit 1 */
109:Src/usart.c **** }
110:Src/usart.c **** }
237 .loc 1 110 1 view .LVU60
238 000a 08BD pop {r3, pc}
239 .LVL9:
240 .L16:
98:Src/usart.c ****
241 .loc 1 98 5 is_stmt 1 view .LVU61
242 000c 064A ldr r2, .L17+4
243 000e 536C ldr r3, [r2, #68]
244 0010 23F01003 bic r3, r3, #16
245 0014 5364 str r3, [r2, #68]
104:Src/usart.c ****
246 .loc 1 104 5 view .LVU62
247 0016 4FF4C061 mov r1, #1536
248 001a 0448 ldr r0, .L17+8
249 .LVL10:
104:Src/usart.c ****
250 .loc 1 104 5 is_stmt 0 view .LVU63
251 001c FFF7FEFF bl HAL_GPIO_DeInit
252 .LVL11:
253 .loc 1 110 1 view .LVU64
254 0020 F3E7 b .L13
255 .L18:
256 0022 00BF .align 2
257 .L17:
258 0024 00100140 .word 1073811456
259 0028 00380240 .word 1073887232
260 002c 00000240 .word 1073872896
261 .cfi_endproc
262 .LFE136:
264 .global huart1
265 .section .bss.huart1,"aw",%nobits
266 .align 2
267 .set .LANCHOR0,. + 0
270 huart1:
ARM GAS /tmp/ccGGuUQz.s page 8
271 0000 00000000 .space 72
271 00000000
271 00000000
271 00000000
271 00000000
272 .text
273 .Letext0:
274 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
275 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
276 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
277 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
278 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
279 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
280 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h"
281 .file 9 "Inc/main.h"
282 .file 10 "Inc/usart.h"
ARM GAS /tmp/ccGGuUQz.s page 9
DEFINED SYMBOLS
*ABS*:0000000000000000 usart.c
/tmp/ccGGuUQz.s:20 .text.MX_USART1_UART_Init:0000000000000000 $t
/tmp/ccGGuUQz.s:26 .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init
/tmp/ccGGuUQz.s:85 .text.MX_USART1_UART_Init:000000000000002c $d
/tmp/ccGGuUQz.s:91 .text.HAL_UART_MspInit:0000000000000000 $t
/tmp/ccGGuUQz.s:97 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit
/tmp/ccGGuUQz.s:204 .text.HAL_UART_MspInit:0000000000000070 $d
/tmp/ccGGuUQz.s:209 .text.HAL_UART_MspDeInit:0000000000000000 $t
/tmp/ccGGuUQz.s:215 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit
/tmp/ccGGuUQz.s:258 .text.HAL_UART_MspDeInit:0000000000000024 $d
/tmp/ccGGuUQz.s:270 .bss.huart1:0000000000000000 huart1
/tmp/ccGGuUQz.s:266 .bss.huart1:0000000000000000 $d
UNDEFINED SYMBOLS
HAL_UART_Init
Error_Handler
HAL_GPIO_Init
HAL_GPIO_DeInit

254
build/wwdg.lst Normal file
View File

@ -0,0 +1,254 @@
ARM GAS /tmp/ccw7539V.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "wwdg.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .section .text.MX_WWDG_Init,"ax",%progbits
20 .align 1
21 .global MX_WWDG_Init
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_WWDG_Init:
27 .LFB134:
28 .file 1 "Src/wwdg.c"
1:Src/wwdg.c **** /* USER CODE BEGIN Header */
2:Src/wwdg.c **** /**
3:Src/wwdg.c **** ******************************************************************************
4:Src/wwdg.c **** * @file wwdg.c
5:Src/wwdg.c **** * @brief This file provides code for the configuration
6:Src/wwdg.c **** * of the WWDG instances.
7:Src/wwdg.c **** ******************************************************************************
8:Src/wwdg.c **** * @attention
9:Src/wwdg.c **** *
10:Src/wwdg.c **** * Copyright (c) 2025 STMicroelectronics.
11:Src/wwdg.c **** * All rights reserved.
12:Src/wwdg.c **** *
13:Src/wwdg.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Src/wwdg.c **** * in the root directory of this software component.
15:Src/wwdg.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Src/wwdg.c **** *
17:Src/wwdg.c **** ******************************************************************************
18:Src/wwdg.c **** */
19:Src/wwdg.c **** /* USER CODE END Header */
20:Src/wwdg.c **** /* Includes ------------------------------------------------------------------*/
21:Src/wwdg.c **** #include "wwdg.h"
22:Src/wwdg.c ****
23:Src/wwdg.c **** /* USER CODE BEGIN 0 */
24:Src/wwdg.c ****
25:Src/wwdg.c **** /* USER CODE END 0 */
26:Src/wwdg.c ****
27:Src/wwdg.c **** WWDG_HandleTypeDef hwwdg;
28:Src/wwdg.c ****
29:Src/wwdg.c **** /* WWDG init function */
30:Src/wwdg.c **** void MX_WWDG_Init(void)
ARM GAS /tmp/ccw7539V.s page 2
31:Src/wwdg.c **** {
29 .loc 1 31 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 0000 08B5 push {r3, lr}
34 .LCFI0:
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
32:Src/wwdg.c ****
33:Src/wwdg.c **** /* USER CODE BEGIN WWDG_Init 0 */
34:Src/wwdg.c ****
35:Src/wwdg.c **** /* USER CODE END WWDG_Init 0 */
36:Src/wwdg.c ****
37:Src/wwdg.c **** /* USER CODE BEGIN WWDG_Init 1 */
38:Src/wwdg.c ****
39:Src/wwdg.c **** /* USER CODE END WWDG_Init 1 */
40:Src/wwdg.c **** hwwdg.Instance = WWDG;
38 .loc 1 40 3 view .LVU1
39 .loc 1 40 18 is_stmt 0 view .LVU2
40 0002 0848 ldr r0, .L5
41 0004 084B ldr r3, .L5+4
42 0006 0360 str r3, [r0]
41:Src/wwdg.c **** hwwdg.Init.Prescaler = WWDG_PRESCALER_1;
43 .loc 1 41 3 is_stmt 1 view .LVU3
44 .loc 1 41 24 is_stmt 0 view .LVU4
45 0008 0023 movs r3, #0
46 000a 4360 str r3, [r0, #4]
42:Src/wwdg.c **** hwwdg.Init.Window = 64;
47 .loc 1 42 3 is_stmt 1 view .LVU5
48 .loc 1 42 21 is_stmt 0 view .LVU6
49 000c 4022 movs r2, #64
50 000e 8260 str r2, [r0, #8]
43:Src/wwdg.c **** hwwdg.Init.Counter = 64;
51 .loc 1 43 3 is_stmt 1 view .LVU7
52 .loc 1 43 22 is_stmt 0 view .LVU8
53 0010 C260 str r2, [r0, #12]
44:Src/wwdg.c **** hwwdg.Init.EWIMode = WWDG_EWI_DISABLE;
54 .loc 1 44 3 is_stmt 1 view .LVU9
55 .loc 1 44 22 is_stmt 0 view .LVU10
56 0012 0361 str r3, [r0, #16]
45:Src/wwdg.c **** if (HAL_WWDG_Init(&hwwdg) != HAL_OK)
57 .loc 1 45 3 is_stmt 1 view .LVU11
58 .loc 1 45 7 is_stmt 0 view .LVU12
59 0014 FFF7FEFF bl HAL_WWDG_Init
60 .LVL0:
61 .loc 1 45 6 view .LVU13
62 0018 00B9 cbnz r0, .L4
63 .L1:
46:Src/wwdg.c **** {
47:Src/wwdg.c **** Error_Handler();
48:Src/wwdg.c **** }
49:Src/wwdg.c **** /* USER CODE BEGIN WWDG_Init 2 */
50:Src/wwdg.c ****
51:Src/wwdg.c **** /* USER CODE END WWDG_Init 2 */
52:Src/wwdg.c ****
ARM GAS /tmp/ccw7539V.s page 3
53:Src/wwdg.c **** }
64 .loc 1 53 1 view .LVU14
65 001a 08BD pop {r3, pc}
66 .L4:
47:Src/wwdg.c **** }
67 .loc 1 47 5 is_stmt 1 view .LVU15
68 001c FFF7FEFF bl Error_Handler
69 .LVL1:
70 .loc 1 53 1 is_stmt 0 view .LVU16
71 0020 FBE7 b .L1
72 .L6:
73 0022 00BF .align 2
74 .L5:
75 0024 00000000 .word .LANCHOR0
76 0028 002C0040 .word 1073753088
77 .cfi_endproc
78 .LFE134:
80 .section .text.HAL_WWDG_MspInit,"ax",%progbits
81 .align 1
82 .global HAL_WWDG_MspInit
83 .syntax unified
84 .thumb
85 .thumb_func
87 HAL_WWDG_MspInit:
88 .LVL2:
89 .LFB135:
54:Src/wwdg.c ****
55:Src/wwdg.c **** void HAL_WWDG_MspInit(WWDG_HandleTypeDef* wwdgHandle)
56:Src/wwdg.c **** {
90 .loc 1 56 1 is_stmt 1 view -0
91 .cfi_startproc
92 @ args = 0, pretend = 0, frame = 8
93 @ frame_needed = 0, uses_anonymous_args = 0
94 @ link register save eliminated.
57:Src/wwdg.c ****
58:Src/wwdg.c **** if(wwdgHandle->Instance==WWDG)
95 .loc 1 58 3 view .LVU18
96 .loc 1 58 16 is_stmt 0 view .LVU19
97 0000 0268 ldr r2, [r0]
98 .loc 1 58 5 view .LVU20
99 0002 094B ldr r3, .L14
100 0004 9A42 cmp r2, r3
101 0006 00D0 beq .L13
102 0008 7047 bx lr
103 .L13:
56:Src/wwdg.c ****
104 .loc 1 56 1 view .LVU21
105 000a 82B0 sub sp, sp, #8
106 .LCFI1:
107 .cfi_def_cfa_offset 8
59:Src/wwdg.c **** {
60:Src/wwdg.c **** /* USER CODE BEGIN WWDG_MspInit 0 */
61:Src/wwdg.c ****
62:Src/wwdg.c **** /* USER CODE END WWDG_MspInit 0 */
63:Src/wwdg.c **** /* WWDG clock enable */
64:Src/wwdg.c **** __HAL_RCC_WWDG_CLK_ENABLE();
108 .loc 1 64 5 is_stmt 1 view .LVU22
ARM GAS /tmp/ccw7539V.s page 4
109 .LBB2:
110 .loc 1 64 5 view .LVU23
111 000c 0023 movs r3, #0
112 000e 0193 str r3, [sp, #4]
113 .loc 1 64 5 view .LVU24
114 0010 064B ldr r3, .L14+4
115 0012 1A6C ldr r2, [r3, #64]
116 0014 42F40062 orr r2, r2, #2048
117 0018 1A64 str r2, [r3, #64]
118 .loc 1 64 5 view .LVU25
119 001a 1B6C ldr r3, [r3, #64]
120 001c 03F40063 and r3, r3, #2048
121 0020 0193 str r3, [sp, #4]
122 .loc 1 64 5 view .LVU26
123 0022 019B ldr r3, [sp, #4]
124 .LBE2:
125 .loc 1 64 5 view .LVU27
65:Src/wwdg.c **** /* USER CODE BEGIN WWDG_MspInit 1 */
66:Src/wwdg.c ****
67:Src/wwdg.c **** /* USER CODE END WWDG_MspInit 1 */
68:Src/wwdg.c **** }
69:Src/wwdg.c **** }
126 .loc 1 69 1 is_stmt 0 view .LVU28
127 0024 02B0 add sp, sp, #8
128 .LCFI2:
129 .cfi_def_cfa_offset 0
130 @ sp needed
131 0026 7047 bx lr
132 .L15:
133 .align 2
134 .L14:
135 0028 002C0040 .word 1073753088
136 002c 00380240 .word 1073887232
137 .cfi_endproc
138 .LFE135:
140 .global hwwdg
141 .section .bss.hwwdg,"aw",%nobits
142 .align 2
143 .set .LANCHOR0,. + 0
146 hwwdg:
147 0000 00000000 .space 20
147 00000000
147 00000000
147 00000000
147 00000000
148 .text
149 .Letext0:
150 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul
151 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h"
152 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
153 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h"
154 .file 6 "Inc/main.h"
155 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
156 .file 8 "Inc/wwdg.h"
ARM GAS /tmp/ccw7539V.s page 5
DEFINED SYMBOLS
*ABS*:0000000000000000 wwdg.c
/tmp/ccw7539V.s:20 .text.MX_WWDG_Init:0000000000000000 $t
/tmp/ccw7539V.s:26 .text.MX_WWDG_Init:0000000000000000 MX_WWDG_Init
/tmp/ccw7539V.s:75 .text.MX_WWDG_Init:0000000000000024 $d
/tmp/ccw7539V.s:81 .text.HAL_WWDG_MspInit:0000000000000000 $t
/tmp/ccw7539V.s:87 .text.HAL_WWDG_MspInit:0000000000000000 HAL_WWDG_MspInit
/tmp/ccw7539V.s:135 .text.HAL_WWDG_MspInit:0000000000000028 $d
/tmp/ccw7539V.s:146 .bss.hwwdg:0000000000000000 hwwdg
/tmp/ccw7539V.s:142 .bss.hwwdg:0000000000000000 $d
UNDEFINED SYMBOLS
HAL_WWDG_Init
Error_Handler