ARM GAS /tmp/cckltHc8.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "system_stm32f4xx.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .section .text.SystemInit,"ax",%progbits 20 .align 1 21 .global SystemInit 22 .syntax unified 23 .thumb 24 .thumb_func 26 SystemInit: 27 .LFB134: 28 .file 1 "Src/system_stm32f4xx.c" 1:Src/system_stm32f4xx.c **** /** 2:Src/system_stm32f4xx.c **** ****************************************************************************** 3:Src/system_stm32f4xx.c **** * @file system_stm32f4xx.c 4:Src/system_stm32f4xx.c **** * @author MCD Application Team 5:Src/system_stm32f4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6:Src/system_stm32f4xx.c **** * 7:Src/system_stm32f4xx.c **** * This file provides two functions and one global variable to be called from 8:Src/system_stm32f4xx.c **** * user application: 9:Src/system_stm32f4xx.c **** * - SystemInit(): This function is called at startup just after reset and 10:Src/system_stm32f4xx.c **** * before branch to main program. This call is made inside 11:Src/system_stm32f4xx.c **** * the "startup_stm32f4xx.s" file. 12:Src/system_stm32f4xx.c **** * 13:Src/system_stm32f4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14:Src/system_stm32f4xx.c **** * by the user application to setup the SysTick 15:Src/system_stm32f4xx.c **** * timer or configure other parameters. 16:Src/system_stm32f4xx.c **** * 17:Src/system_stm32f4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18:Src/system_stm32f4xx.c **** * be called whenever the core clock is changed 19:Src/system_stm32f4xx.c **** * during program execution. 20:Src/system_stm32f4xx.c **** * 21:Src/system_stm32f4xx.c **** * 22:Src/system_stm32f4xx.c **** ****************************************************************************** 23:Src/system_stm32f4xx.c **** * @attention 24:Src/system_stm32f4xx.c **** * 25:Src/system_stm32f4xx.c **** * Copyright (c) 2017 STMicroelectronics. 26:Src/system_stm32f4xx.c **** * All rights reserved. 27:Src/system_stm32f4xx.c **** * 28:Src/system_stm32f4xx.c **** * This software is licensed under terms that can be found in the LICENSE file 29:Src/system_stm32f4xx.c **** * in the root directory of this software component. 30:Src/system_stm32f4xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. ARM GAS /tmp/cckltHc8.s page 2 31:Src/system_stm32f4xx.c **** * 32:Src/system_stm32f4xx.c **** ****************************************************************************** 33:Src/system_stm32f4xx.c **** */ 34:Src/system_stm32f4xx.c **** 35:Src/system_stm32f4xx.c **** /** @addtogroup CMSIS 36:Src/system_stm32f4xx.c **** * @{ 37:Src/system_stm32f4xx.c **** */ 38:Src/system_stm32f4xx.c **** 39:Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system 40:Src/system_stm32f4xx.c **** * @{ 41:Src/system_stm32f4xx.c **** */ 42:Src/system_stm32f4xx.c **** 43:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes 44:Src/system_stm32f4xx.c **** * @{ 45:Src/system_stm32f4xx.c **** */ 46:Src/system_stm32f4xx.c **** 47:Src/system_stm32f4xx.c **** 48:Src/system_stm32f4xx.c **** #include "stm32f4xx.h" 49:Src/system_stm32f4xx.c **** 50:Src/system_stm32f4xx.c **** #if !defined (HSE_VALUE) 51:Src/system_stm32f4xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ 52:Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */ 53:Src/system_stm32f4xx.c **** 54:Src/system_stm32f4xx.c **** #if !defined (HSI_VALUE) 55:Src/system_stm32f4xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 56:Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */ 57:Src/system_stm32f4xx.c **** 58:Src/system_stm32f4xx.c **** /** 59:Src/system_stm32f4xx.c **** * @} 60:Src/system_stm32f4xx.c **** */ 61:Src/system_stm32f4xx.c **** 62:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 63:Src/system_stm32f4xx.c **** * @{ 64:Src/system_stm32f4xx.c **** */ 65:Src/system_stm32f4xx.c **** 66:Src/system_stm32f4xx.c **** /** 67:Src/system_stm32f4xx.c **** * @} 68:Src/system_stm32f4xx.c **** */ 69:Src/system_stm32f4xx.c **** 70:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines 71:Src/system_stm32f4xx.c **** * @{ 72:Src/system_stm32f4xx.c **** */ 73:Src/system_stm32f4xx.c **** 74:Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/ 75:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 76:Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 77:Src/system_stm32f4xx.c **** || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 78:Src/system_stm32f4xx.c **** || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 79:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */ 80:Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx || 81:Src/system_stm32f4xx.c **** STM32F412Zx || STM32F412Vx */ 82:Src/system_stm32f4xx.c **** 83:Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 84:Src/system_stm32f4xx.c **** || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 85:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */ 86:Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || 87:Src/system_stm32f4xx.c **** STM32F479xx */ ARM GAS /tmp/cckltHc8.s page 3 88:Src/system_stm32f4xx.c **** 89:Src/system_stm32f4xx.c **** /* Note: Following vector table addresses must be defined in line with linker 90:Src/system_stm32f4xx.c **** configuration. */ 91:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table 92:Src/system_stm32f4xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic 93:Src/system_stm32f4xx.c **** remap of boot address selected */ 94:Src/system_stm32f4xx.c **** /* #define USER_VECT_TAB_ADDRESS */ 95:Src/system_stm32f4xx.c **** 96:Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 97:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table 98:Src/system_stm32f4xx.c **** in Sram else user remap will be done in Flash. */ 99:Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */ 100:Src/system_stm32f4xx.c **** #if defined(VECT_TAB_SRAM) 101:Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 102:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */ 103:Src/system_stm32f4xx.c **** #else 104:Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 105:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */ 106:Src/system_stm32f4xx.c **** #endif /* VECT_TAB_SRAM */ 107:Src/system_stm32f4xx.c **** #if !defined(VECT_TAB_OFFSET) 108:Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. 109:Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */ 110:Src/system_stm32f4xx.c **** #endif /* VECT_TAB_OFFSET */ 111:Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 112:Src/system_stm32f4xx.c **** /******************************************************************************/ 113:Src/system_stm32f4xx.c **** 114:Src/system_stm32f4xx.c **** /** 115:Src/system_stm32f4xx.c **** * @} 116:Src/system_stm32f4xx.c **** */ 117:Src/system_stm32f4xx.c **** 118:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros 119:Src/system_stm32f4xx.c **** * @{ 120:Src/system_stm32f4xx.c **** */ 121:Src/system_stm32f4xx.c **** 122:Src/system_stm32f4xx.c **** /** 123:Src/system_stm32f4xx.c **** * @} 124:Src/system_stm32f4xx.c **** */ 125:Src/system_stm32f4xx.c **** 126:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables 127:Src/system_stm32f4xx.c **** * @{ 128:Src/system_stm32f4xx.c **** */ 129:Src/system_stm32f4xx.c **** /* This variable is updated in three ways: 130:Src/system_stm32f4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() 131:Src/system_stm32f4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 132:Src/system_stm32f4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 133:Src/system_stm32f4xx.c **** Note: If you use this function to configure the system clock; then there 134:Src/system_stm32f4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock 135:Src/system_stm32f4xx.c **** variable is updated automatically. 136:Src/system_stm32f4xx.c **** */ 137:Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000; 138:Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 139:Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 140:Src/system_stm32f4xx.c **** /** 141:Src/system_stm32f4xx.c **** * @} 142:Src/system_stm32f4xx.c **** */ 143:Src/system_stm32f4xx.c **** 144:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes ARM GAS /tmp/cckltHc8.s page 4 145:Src/system_stm32f4xx.c **** * @{ 146:Src/system_stm32f4xx.c **** */ 147:Src/system_stm32f4xx.c **** 148:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 149:Src/system_stm32f4xx.c **** static void SystemInit_ExtMemCtl(void); 150:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 151:Src/system_stm32f4xx.c **** 152:Src/system_stm32f4xx.c **** /** 153:Src/system_stm32f4xx.c **** * @} 154:Src/system_stm32f4xx.c **** */ 155:Src/system_stm32f4xx.c **** 156:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions 157:Src/system_stm32f4xx.c **** * @{ 158:Src/system_stm32f4xx.c **** */ 159:Src/system_stm32f4xx.c **** 160:Src/system_stm32f4xx.c **** /** 161:Src/system_stm32f4xx.c **** * @brief Setup the microcontroller system 162:Src/system_stm32f4xx.c **** * Initialize the FPU setting, vector table location and External memory 163:Src/system_stm32f4xx.c **** * configuration. 164:Src/system_stm32f4xx.c **** * @param None 165:Src/system_stm32f4xx.c **** * @retval None 166:Src/system_stm32f4xx.c **** */ 167:Src/system_stm32f4xx.c **** void SystemInit(void) 168:Src/system_stm32f4xx.c **** { 29 .loc 1 168 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 @ link register save eliminated. 169:Src/system_stm32f4xx.c **** /* FPU settings ------------------------------------------------------------*/ 170:Src/system_stm32f4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 171:Src/system_stm32f4xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 34 .loc 1 171 5 view .LVU1 35 .loc 1 171 16 is_stmt 0 view .LVU2 36 0000 034A ldr r2, .L2 37 0002 D2F88830 ldr r3, [r2, #136] 38 0006 43F47003 orr r3, r3, #15728640 39 000a C2F88830 str r3, [r2, #136] 172:Src/system_stm32f4xx.c **** #endif 173:Src/system_stm32f4xx.c **** 174:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 175:Src/system_stm32f4xx.c **** SystemInit_ExtMemCtl(); 176:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 177:Src/system_stm32f4xx.c **** 178:Src/system_stm32f4xx.c **** /* Configure the Vector Table location -------------------------------------*/ 179:Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 180:Src/system_stm32f4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 181:Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 182:Src/system_stm32f4xx.c **** } 40 .loc 1 182 1 view .LVU3 41 000e 7047 bx lr 42 .L3: 43 .align 2 44 .L2: 45 0010 00ED00E0 .word -536810240 46 .cfi_endproc 47 .LFE134: ARM GAS /tmp/cckltHc8.s page 5 49 .section .text.SystemCoreClockUpdate,"ax",%progbits 50 .align 1 51 .global SystemCoreClockUpdate 52 .syntax unified 53 .thumb 54 .thumb_func 56 SystemCoreClockUpdate: 57 .LFB135: 183:Src/system_stm32f4xx.c **** 184:Src/system_stm32f4xx.c **** /** 185:Src/system_stm32f4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. 186:Src/system_stm32f4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can 187:Src/system_stm32f4xx.c **** * be used by the user application to setup the SysTick timer or configure 188:Src/system_stm32f4xx.c **** * other parameters. 189:Src/system_stm32f4xx.c **** * 190:Src/system_stm32f4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called 191:Src/system_stm32f4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration 192:Src/system_stm32f4xx.c **** * based on this variable will be incorrect. 193:Src/system_stm32f4xx.c **** * 194:Src/system_stm32f4xx.c **** * @note - The system frequency computed by this function is not the real 195:Src/system_stm32f4xx.c **** * frequency in the chip. It is calculated based on the predefined 196:Src/system_stm32f4xx.c **** * constant and the selected clock source: 197:Src/system_stm32f4xx.c **** * 198:Src/system_stm32f4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 199:Src/system_stm32f4xx.c **** * 200:Src/system_stm32f4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 201:Src/system_stm32f4xx.c **** * 202:Src/system_stm32f4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 203:Src/system_stm32f4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. 204:Src/system_stm32f4xx.c **** * 205:Src/system_stm32f4xx.c **** * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 206:Src/system_stm32f4xx.c **** * 16 MHz) but the real value may vary depending on the variations 207:Src/system_stm32f4xx.c **** * in voltage and temperature. 208:Src/system_stm32f4xx.c **** * 209:Src/system_stm32f4xx.c **** * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value 210:Src/system_stm32f4xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE 211:Src/system_stm32f4xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function 212:Src/system_stm32f4xx.c **** * may have wrong result. 213:Src/system_stm32f4xx.c **** * 214:Src/system_stm32f4xx.c **** * - The result of this function could be not correct when using fractional 215:Src/system_stm32f4xx.c **** * value for HSE crystal. 216:Src/system_stm32f4xx.c **** * 217:Src/system_stm32f4xx.c **** * @param None 218:Src/system_stm32f4xx.c **** * @retval None 219:Src/system_stm32f4xx.c **** */ 220:Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void) 221:Src/system_stm32f4xx.c **** { 58 .loc 1 221 1 is_stmt 1 view -0 59 .cfi_startproc 60 @ args = 0, pretend = 0, frame = 0 61 @ frame_needed = 0, uses_anonymous_args = 0 62 @ link register save eliminated. 222:Src/system_stm32f4xx.c **** uint32_t tmp, pllvco, pllp, pllsource, pllm; 63 .loc 1 222 3 view .LVU5 223:Src/system_stm32f4xx.c **** 224:Src/system_stm32f4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ 225:Src/system_stm32f4xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; ARM GAS /tmp/cckltHc8.s page 6 64 .loc 1 225 3 view .LVU6 65 .loc 1 225 12 is_stmt 0 view .LVU7 66 0000 224B ldr r3, .L12 67 0002 9B68 ldr r3, [r3, #8] 68 .loc 1 225 7 view .LVU8 69 0004 03F00C03 and r3, r3, #12 70 .LVL0: 226:Src/system_stm32f4xx.c **** 227:Src/system_stm32f4xx.c **** switch (tmp) 71 .loc 1 227 3 is_stmt 1 view .LVU9 72 0008 042B cmp r3, #4 73 000a 14D0 beq .L5 74 000c 082B cmp r3, #8 75 000e 16D0 beq .L6 76 0010 1BB1 cbz r3, .L11 228:Src/system_stm32f4xx.c **** { 229:Src/system_stm32f4xx.c **** case 0x00: /* HSI used as system clock source */ 230:Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE; 231:Src/system_stm32f4xx.c **** break; 232:Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */ 233:Src/system_stm32f4xx.c **** SystemCoreClock = HSE_VALUE; 234:Src/system_stm32f4xx.c **** break; 235:Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */ 236:Src/system_stm32f4xx.c **** 237:Src/system_stm32f4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 238:Src/system_stm32f4xx.c **** SYSCLK = PLL_VCO / PLL_P 239:Src/system_stm32f4xx.c **** */ 240:Src/system_stm32f4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 241:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 242:Src/system_stm32f4xx.c **** 243:Src/system_stm32f4xx.c **** if (pllsource != 0) 244:Src/system_stm32f4xx.c **** { 245:Src/system_stm32f4xx.c **** /* HSE used as PLL clock source */ 246:Src/system_stm32f4xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 247:Src/system_stm32f4xx.c **** } 248:Src/system_stm32f4xx.c **** else 249:Src/system_stm32f4xx.c **** { 250:Src/system_stm32f4xx.c **** /* HSI used as PLL clock source */ 251:Src/system_stm32f4xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 252:Src/system_stm32f4xx.c **** } 253:Src/system_stm32f4xx.c **** 254:Src/system_stm32f4xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 255:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 256:Src/system_stm32f4xx.c **** break; 257:Src/system_stm32f4xx.c **** default: 258:Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE; 77 .loc 1 258 7 view .LVU10 78 .loc 1 258 23 is_stmt 0 view .LVU11 79 0012 1F4B ldr r3, .L12+4 80 .LVL1: 81 .loc 1 258 23 view .LVU12 82 0014 1F4A ldr r2, .L12+8 83 0016 1A60 str r2, [r3] 259:Src/system_stm32f4xx.c **** break; 84 .loc 1 259 7 is_stmt 1 view .LVU13 85 0018 02E0 b .L8 86 .LVL2: ARM GAS /tmp/cckltHc8.s page 7 87 .L11: 230:Src/system_stm32f4xx.c **** break; 88 .loc 1 230 7 view .LVU14 230:Src/system_stm32f4xx.c **** break; 89 .loc 1 230 23 is_stmt 0 view .LVU15 90 001a 1D4B ldr r3, .L12+4 91 .LVL3: 230:Src/system_stm32f4xx.c **** break; 92 .loc 1 230 23 view .LVU16 93 001c 1D4A ldr r2, .L12+8 94 001e 1A60 str r2, [r3] 231:Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */ 95 .loc 1 231 7 is_stmt 1 view .LVU17 96 .L8: 260:Src/system_stm32f4xx.c **** } 261:Src/system_stm32f4xx.c **** /* Compute HCLK frequency --------------------------------------------------*/ 262:Src/system_stm32f4xx.c **** /* Get HCLK prescaler */ 263:Src/system_stm32f4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 97 .loc 1 263 3 view .LVU18 98 .loc 1 263 28 is_stmt 0 view .LVU19 99 0020 1A4B ldr r3, .L12 100 0022 9B68 ldr r3, [r3, #8] 101 .loc 1 263 52 view .LVU20 102 0024 C3F30313 ubfx r3, r3, #4, #4 103 .loc 1 263 22 view .LVU21 104 0028 1B4A ldr r2, .L12+12 105 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2 106 .LVL4: 264:Src/system_stm32f4xx.c **** /* HCLK frequency */ 265:Src/system_stm32f4xx.c **** SystemCoreClock >>= tmp; 107 .loc 1 265 3 is_stmt 1 view .LVU22 108 .loc 1 265 19 is_stmt 0 view .LVU23 109 002c 184A ldr r2, .L12+4 110 002e 1368 ldr r3, [r2] 111 0030 CB40 lsrs r3, r3, r1 112 0032 1360 str r3, [r2] 266:Src/system_stm32f4xx.c **** } 113 .loc 1 266 1 view .LVU24 114 0034 7047 bx lr 115 .LVL5: 116 .L5: 233:Src/system_stm32f4xx.c **** break; 117 .loc 1 233 7 is_stmt 1 view .LVU25 233:Src/system_stm32f4xx.c **** break; 118 .loc 1 233 23 is_stmt 0 view .LVU26 119 0036 164B ldr r3, .L12+4 120 .LVL6: 233:Src/system_stm32f4xx.c **** break; 121 .loc 1 233 23 view .LVU27 122 0038 184A ldr r2, .L12+16 123 003a 1A60 str r2, [r3] 234:Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */ 124 .loc 1 234 7 is_stmt 1 view .LVU28 125 003c F0E7 b .L8 126 .LVL7: 127 .L6: 240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; ARM GAS /tmp/cckltHc8.s page 8 128 .loc 1 240 7 view .LVU29 240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 129 .loc 1 240 23 is_stmt 0 view .LVU30 130 003e 134B ldr r3, .L12 131 .LVL8: 240:Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 132 .loc 1 240 23 view .LVU31 133 0040 5968 ldr r1, [r3, #4] 134 .LVL9: 241:Src/system_stm32f4xx.c **** 135 .loc 1 241 7 is_stmt 1 view .LVU32 241:Src/system_stm32f4xx.c **** 136 .loc 1 241 17 is_stmt 0 view .LVU33 137 0042 5A68 ldr r2, [r3, #4] 241:Src/system_stm32f4xx.c **** 138 .loc 1 241 12 view .LVU34 139 0044 02F03F02 and r2, r2, #63 140 .LVL10: 243:Src/system_stm32f4xx.c **** { 141 .loc 1 243 7 is_stmt 1 view .LVU35 243:Src/system_stm32f4xx.c **** { 142 .loc 1 243 10 is_stmt 0 view .LVU36 143 0048 11F4800F tst r1, #4194304 144 004c 13D0 beq .L9 246:Src/system_stm32f4xx.c **** } 145 .loc 1 246 9 is_stmt 1 view .LVU37 246:Src/system_stm32f4xx.c **** } 146 .loc 1 246 29 is_stmt 0 view .LVU38 147 004e 134B ldr r3, .L12+16 148 0050 B3FBF2F3 udiv r3, r3, r2 246:Src/system_stm32f4xx.c **** } 149 .loc 1 246 44 view .LVU39 150 0054 0D4A ldr r2, .L12 151 .LVL11: 246:Src/system_stm32f4xx.c **** } 152 .loc 1 246 44 view .LVU40 153 0056 5268 ldr r2, [r2, #4] 246:Src/system_stm32f4xx.c **** } 154 .loc 1 246 74 view .LVU41 155 0058 C2F38812 ubfx r2, r2, #6, #9 246:Src/system_stm32f4xx.c **** } 156 .loc 1 246 16 view .LVU42 157 005c 02FB03F3 mul r3, r2, r3 158 .LVL12: 159 .L10: 254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 160 .loc 1 254 7 is_stmt 1 view .LVU43 254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 161 .loc 1 254 20 is_stmt 0 view .LVU44 162 0060 0A4A ldr r2, .L12 163 0062 5268 ldr r2, [r2, #4] 254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 164 .loc 1 254 50 view .LVU45 165 0064 C2F30142 ubfx r2, r2, #16, #2 254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 166 .loc 1 254 56 view .LVU46 167 0068 0132 adds r2, r2, #1 ARM GAS /tmp/cckltHc8.s page 9 254:Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp; 168 .loc 1 254 12 view .LVU47 169 006a 5200 lsls r2, r2, #1 170 .LVL13: 255:Src/system_stm32f4xx.c **** break; 171 .loc 1 255 7 is_stmt 1 view .LVU48 255:Src/system_stm32f4xx.c **** break; 172 .loc 1 255 31 is_stmt 0 view .LVU49 173 006c B3FBF2F3 udiv r3, r3, r2 174 .LVL14: 255:Src/system_stm32f4xx.c **** break; 175 .loc 1 255 23 view .LVU50 176 0070 074A ldr r2, .L12+4 177 .LVL15: 255:Src/system_stm32f4xx.c **** break; 178 .loc 1 255 23 view .LVU51 179 0072 1360 str r3, [r2] 256:Src/system_stm32f4xx.c **** default: 180 .loc 1 256 7 is_stmt 1 view .LVU52 181 0074 D4E7 b .L8 182 .LVL16: 183 .L9: 251:Src/system_stm32f4xx.c **** } 184 .loc 1 251 9 view .LVU53 251:Src/system_stm32f4xx.c **** } 185 .loc 1 251 29 is_stmt 0 view .LVU54 186 0076 074B ldr r3, .L12+8 187 0078 B3FBF2F3 udiv r3, r3, r2 251:Src/system_stm32f4xx.c **** } 188 .loc 1 251 44 view .LVU55 189 007c 034A ldr r2, .L12 190 .LVL17: 251:Src/system_stm32f4xx.c **** } 191 .loc 1 251 44 view .LVU56 192 007e 5268 ldr r2, [r2, #4] 251:Src/system_stm32f4xx.c **** } 193 .loc 1 251 74 view .LVU57 194 0080 C2F38812 ubfx r2, r2, #6, #9 251:Src/system_stm32f4xx.c **** } 195 .loc 1 251 16 view .LVU58 196 0084 02FB03F3 mul r3, r2, r3 197 .LVL18: 251:Src/system_stm32f4xx.c **** } 198 .loc 1 251 16 view .LVU59 199 0088 EAE7 b .L10 200 .L13: 201 008a 00BF .align 2 202 .L12: 203 008c 00380240 .word 1073887232 204 0090 00000000 .word .LANCHOR0 205 0094 0024F400 .word 16000000 206 0098 00000000 .word .LANCHOR1 207 009c 00127A00 .word 8000000 208 .cfi_endproc 209 .LFE135: 211 .global APBPrescTable 212 .global AHBPrescTable ARM GAS /tmp/cckltHc8.s page 10 213 .global SystemCoreClock 214 .section .data.SystemCoreClock,"aw" 215 .align 2 216 .set .LANCHOR0,. + 0 219 SystemCoreClock: 220 0000 0024F400 .word 16000000 221 .section .rodata.AHBPrescTable,"a" 222 .align 2 223 .set .LANCHOR1,. + 0 226 AHBPrescTable: 227 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" 227 00000000 227 01020304 227 06 228 000d 070809 .ascii "\007\010\011" 229 .section .rodata.APBPrescTable,"a" 230 .align 2 233 APBPrescTable: 234 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" 234 01020304 235 .text 236 .Letext0: 237 .file 2 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/machine/_defaul 238 .file 3 "/home/jfen/toolchain/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/sys/_stdint.h" 239 .file 4 "Drivers/CMSIS/Include/core_cm4.h" 240 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" 241 .file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h" ARM GAS /tmp/cckltHc8.s page 11 DEFINED SYMBOLS *ABS*:0000000000000000 system_stm32f4xx.c /tmp/cckltHc8.s:20 .text.SystemInit:0000000000000000 $t /tmp/cckltHc8.s:26 .text.SystemInit:0000000000000000 SystemInit /tmp/cckltHc8.s:45 .text.SystemInit:0000000000000010 $d /tmp/cckltHc8.s:50 .text.SystemCoreClockUpdate:0000000000000000 $t /tmp/cckltHc8.s:56 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate /tmp/cckltHc8.s:203 .text.SystemCoreClockUpdate:000000000000008c $d /tmp/cckltHc8.s:233 .rodata.APBPrescTable:0000000000000000 APBPrescTable /tmp/cckltHc8.s:226 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable /tmp/cckltHc8.s:219 .data.SystemCoreClock:0000000000000000 SystemCoreClock /tmp/cckltHc8.s:215 .data.SystemCoreClock:0000000000000000 $d /tmp/cckltHc8.s:222 .rodata.AHBPrescTable:0000000000000000 $d /tmp/cckltHc8.s:230 .rodata.APBPrescTable:0000000000000000 $d NO UNDEFINED SYMBOLS