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218
Libraries/HAL_Drivers/drivers/drv_nand.c
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218
Libraries/HAL_Drivers/drivers/drv_nand.c
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-09-28 mingmiaojing first version
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*/
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#include <rtconfig.h>
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#ifdef BSP_USING_NAND1
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#include <board.h>
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#include "drv_nand.h"
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#include "drv_config.h"
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#include <lpm.h>
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#define NAND_PAGE_SIZE ((uint16_t)2048)
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#define NAND1_RW_TEST
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#ifndef RT_FIOGETXIPADDR
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#define RT_FIOGETXIPADDR 0x52540001U
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#endif
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struct rt_device _hw_nand1;
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NAND_HandleTypeDef hnand1;
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/* FSMC initialization function */
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static void rt_nand_init(void)
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{
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/* USER CODE BEGIN FSMC_Init 0 */
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/* USER CODE END FSMC_Init 0 */
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FSMC_NAND_PCC_TimingTypeDef ComSpaceTiming = {0};
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FSMC_NAND_PCC_TimingTypeDef AttSpaceTiming = {0};
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/* USER CODE BEGIN FSMC_Init 1 */
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/* USER CODE END FSMC_Init 1 */
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/** Perform the NAND1 memory initialization sequence
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*/
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hnand1.Instance = FSMC_NAND_DEVICE;
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/* hnand1.Init */
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hnand1.Init.NandBank = FSMC_NAND_BANK2;
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hnand1.Init.Waitfeature = FSMC_NAND_PCC_WAIT_FEATURE_ENABLE;
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hnand1.Init.MemoryDataWidth = FSMC_NAND_PCC_MEM_BUS_WIDTH_8;
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hnand1.Init.EccComputation = FSMC_NAND_ECC_ENABLE;
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hnand1.Init.ECCPageSize = FSMC_NAND_ECC_PAGE_SIZE_512BYTE;
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hnand1.Init.TCLRSetupTime = 0;
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hnand1.Init.TARSetupTime = 0;
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/* hnand1.Config */
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hnand1.Config.PageSize = NAND_PAGE_SIZE;
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hnand1.Config.SpareAreaSize = 64;
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hnand1.Config.BlockSize = 64;
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hnand1.Config.BlockNbr = 1024;
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hnand1.Config.PlaneNbr = 1;
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hnand1.Config.PlaneSize = 1024;
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hnand1.Config.ExtraCommandEnable = DISABLE;
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/* ComSpaceTiming */
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ComSpaceTiming.SetupTime = 4;
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ComSpaceTiming.WaitSetupTime = 3;
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ComSpaceTiming.HoldSetupTime = 2;
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ComSpaceTiming.HiZSetupTime = 4;
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/* AttSpaceTiming */
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AttSpaceTiming.SetupTime = 4;
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AttSpaceTiming.WaitSetupTime = 3;
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AttSpaceTiming.HoldSetupTime = 2;
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AttSpaceTiming.HiZSetupTime = 4;
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if (HAL_NAND_Init(&hnand1, &ComSpaceTiming, &AttSpaceTiming) != HAL_OK)
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{
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Error_Handler( );
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}
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/** Disconnect NADV
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*/
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__HAL_AFIO_FSMCNADV_DISCONNECTED();
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/* USER CODE BEGIN FSMC_Init 2 */
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/* USER CODE END FSMC_Init 2 */
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}
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rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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rt_err_t rt_nand_control(rt_device_t dev, int cmd, void *args)
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{
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if(RT_DEVICE_CTRL_BLK_GETGEOME == cmd)
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{
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struct rt_device_blk_geometry *geometry = (struct rt_device_blk_geometry *)args;
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geometry->bytes_per_sector = 2048;
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geometry->sector_count = 64 * 1024;
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geometry->block_size = 2048 * 64;
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return RT_EOK;
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}
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else if(RT_FIOGETXIPADDR == cmd)
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{
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uint32_t *start_addr = (uint32_t *)args;
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*start_addr = 0;
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return RT_EOK;
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}
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else if(RT_DEVICE_CTRL_BLK_ERASE == cmd)
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{
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uint32_t *blk = (uint32_t *)args;
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NAND_AddressTypeDef Addr;
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Addr.Plane = 0x00;
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Addr.Block = *blk;
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Addr.Page = 0x00;
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HAL_NAND_Erase_Block(&hnand1,&Addr);
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return RT_EOK;
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}
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return -RT_ERROR;
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}
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/*pos: sector offset size: page count*/
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rt_ssize_t rt_nand_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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uint32_t page_cnt = size;
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NAND_AddressTypeDef ReadAddr;
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ReadAddr.Page = pos%64;
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ReadAddr.Plane = 0;
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ReadAddr.Block = pos/64;
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HAL_NAND_Read_Page(&hnand1, &ReadAddr, (uint8_t *)buffer, page_cnt);
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return RT_EOK;
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}
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rt_ssize_t rt_nand_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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uint32_t page_cnt = size;
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NAND_AddressTypeDef WriteAddr;
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WriteAddr.Page = pos%64;
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WriteAddr.Plane = 0;
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WriteAddr.Block = pos/64;
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HAL_NAND_Write_Page(&hnand1, &WriteAddr, (uint8_t *)buffer, page_cnt);
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return RT_EOK;
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}
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static int stm32_nand1_init(void)
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{
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NAND_IDTypeDef NAND_ID;
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rt_nand_init();
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HAL_NAND_Read_ID(&hnand1, &NAND_ID);
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rt_kprintf("Nand Flash ID = 0x%02X,0x%02X,0x%02X,0x%02X",
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NAND_ID.Maker_Id, NAND_ID.Device_Id,
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NAND_ID.Third_Id, NAND_ID.Fourth_Id);
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#ifdef NAND1_RW_TEST
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uint32_t i = 0;
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static uint8_t TxBuffer [NAND_PAGE_SIZE];
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static uint8_t RxBuffer [NAND_PAGE_SIZE];
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NAND_AddressTypeDef WriteReadAddr;
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WriteReadAddr.Plane = 0x00;
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WriteReadAddr.Block = 0x00;
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WriteReadAddr.Page = 0x00;
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/* Erase the NAND first Block */
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for(i = 0; i < 64; i++)
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{
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WriteReadAddr.Block = i;
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HAL_NAND_Erase_Block(&hnand1,&WriteReadAddr);
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}
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// /* Fill the buffer to send */
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// for (i = 0; i < NAND_PAGE_SIZE; i++ )
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// {
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// TxBuffer[i] = i;
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// }
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//
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// /* Write data to FMC NAND memory */
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// HAL_NAND_Write_Page(&hnand1, &WriteReadAddr, TxBuffer, 1);
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// rt_kprintf("\r\nWritten to the number:\r\n");
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// for(i = 0; i < 2048; i++)
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// {
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// rt_kprintf("0x%02X \t",TxBuffer[i]);
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// }
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// rt_kprintf("\n");
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// HAL_Delay(100);
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/* Read data from FMC NAND memory */
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WriteReadAddr.Block = 0;
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HAL_NAND_Read_Page(&hnand1, &WriteReadAddr, RxBuffer, 1);
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rt_kprintf("\r\nRead receive: \r\n");
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for(i = 0; i < 16; i++)
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{
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rt_kprintf("0x%02X \t",RxBuffer[i]);
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}
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rt_kprintf("\n");
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#endif
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//_hw_nand1.ops = &_hw_nand1;
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_hw_nand1.type = RT_Device_Class_MTD;
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_hw_nand1.init = RT_NULL;//rt_nand_init
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_hw_nand1.open = rt_nand_open;
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_hw_nand1.close = RT_NULL;
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_hw_nand1.read = rt_nand_read;
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_hw_nand1.write = rt_nand_write;
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_hw_nand1.control = rt_nand_control;
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_hw_nand1.user_data = RT_NULL;
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rt_device_register(&_hw_nand1,"nand1", RT_DEVICE_FLAG_RDWR);
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rt_kprintf("nand1 init done\n");
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lpm_init();
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lpm_dev_blk_append(&_hw_nand1);
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return 0;
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}
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INIT_BOARD_EXPORT(stm32_nand1_init);
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#endif
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