原始版本
This commit is contained in:
冯佳
57
RT_Thread/components/drivers/pic/Kconfig
Normal file
57
RT_Thread/components/drivers/pic/Kconfig
Normal file
@ -0,0 +1,57 @@
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menuconfig RT_USING_PIC
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bool "Using Programmable Interrupt Controller (PIC)"
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select RT_USING_ADT
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select RT_USING_ADT_BITMAP
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depends on RT_USING_DM
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default n
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config RT_USING_PIC_STATISTICS
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bool "Enable ISR execution time statistics"
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depends on RT_USING_PIC
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depends on RT_USING_KTIME
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depends on RT_USING_INTERRUPT_INFO
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default n
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config MAX_HANDLERS
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int "IRQ max handlers"
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depends on RT_USING_PIC
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range 1 4294967294
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default 256
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config RT_PIC_ARM_GIC
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bool "ARM GICv2/v1"
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depends on RT_USING_PIC
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select RT_USING_OFW
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default n
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config RT_PIC_ARM_GIC_V2M
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bool "ARM GIC V2M" if RT_PIC_ARM_GIC && RT_PCI_MSI
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depends on RT_USING_OFW
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default n
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config RT_PIC_ARM_GIC_V3
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bool "ARM GICv3"
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depends on RT_USING_PIC
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select RT_USING_OFW
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default n
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config RT_PIC_ARM_GIC_V3_ITS
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bool "ARM GICv3 ITS (Interrupt Translation Service)" if RT_PIC_ARM_GIC_V3 && RT_PCI_MSI
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depends on RT_USING_OFW
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select RT_USING_ADT_REF
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default n
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config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX
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int "IRQ maximum used"
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depends on RT_PIC_ARM_GIC_V3_ITS
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default 127 if ARCH_CPU_64BIT
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default 63
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help
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Recommended to be based on the bit length (full bits) of maximum usage.
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config RT_PIC_ARM_GIC_MAX_NR
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int
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depends on RT_USING_PIC
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depends on RT_PIC_ARM_GIC
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default 2 if SOC_REALVIEW
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default 1
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30
RT_Thread/components/drivers/pic/SConscript
Normal file
30
RT_Thread/components/drivers/pic/SConscript
Normal file
@ -0,0 +1,30 @@
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from building import *
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group = []
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if not GetDepend(['RT_USING_PIC']):
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Return('group')
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cwd = GetCurrentDir()
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CPPPATH = [cwd + '/../include']
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src = ['pic.c', 'pic_rthw.c']
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if GetDepend(['RT_PIC_ARM_GIC']) or GetDepend(['RT_PIC_ARM_GIC_V3']):
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src += ['pic-gic-common.c']
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if GetDepend(['RT_PIC_ARM_GIC']):
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src += ['pic-gicv2.c']
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if GetDepend(['RT_PIC_ARM_GIC_V2M']):
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src += ['pic-gicv2m.c']
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if GetDepend(['RT_PIC_ARM_GIC_V3']):
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src += ['pic-gicv3.c']
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if GetDepend(['RT_PIC_ARM_GIC_V3_ITS']):
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src += ['pic-gicv3-its.c']
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group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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184
RT_Thread/components/drivers/pic/pic-gic-common.c
Normal file
184
RT_Thread/components/drivers/pic/pic-gic-common.c
Normal file
@ -0,0 +1,184 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-01-30 GuEe-GUI first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#define DBG_TAG "pic.gic*"
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#define DBG_LVL DBG_LOG
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#include <rtdbg.h>
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#include <drivers/pic.h>
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#include "pic-gicv2.h"
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#include "pic-gic-common.h"
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void gic_common_init_quirk_ofw(const struct rt_ofw_node *ic_np, const struct gic_quirk *quirks, void *data)
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{
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for (; quirks->desc; ++quirks)
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{
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if (!quirks->compatible || !rt_ofw_node_is_compatible(ic_np, quirks->compatible))
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{
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continue;
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}
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RT_ASSERT(quirks->init != RT_NULL);
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if (!quirks->init(data))
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{
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LOG_I("Enable workaround for %s", quirks->desc);
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}
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}
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}
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void gic_common_init_quirk_hw(rt_uint32_t iidr, const struct gic_quirk *quirks, void *data)
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{
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for (; quirks->desc; ++quirks)
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{
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if (quirks->compatible)
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{
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continue;
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}
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if (quirks->iidr == (iidr & quirks->iidr_mask))
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{
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RT_ASSERT(quirks->init != RT_NULL);
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if (!quirks->init(data))
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{
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LOG_I("Enable workaround for %s", quirks->desc);
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}
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}
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}
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}
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void gic_common_sgi_config(void *base, void *data, int irq_base)
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{
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#ifdef RT_USING_SMP
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if (irq_base < 2)
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{
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struct rt_pic_irq *pirq;
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#define DECLARE_GIC_IPI(ipi, hwirq) \
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rt_pic_config_ipi(data, ipi, hwirq); \
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pirq = rt_pic_find_ipi(data, ipi); \
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pirq->mode = RT_IRQ_MODE_EDGE_RISING; \
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DECLARE_GIC_IPI(RT_SCHEDULE_IPI, RT_SCHEDULE_IPI);
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DECLARE_GIC_IPI(RT_STOP_IPI, RT_STOP_IPI);
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DECLARE_GIC_IPI(RT_SMP_CALL_IPI, RT_SMP_CALL_IPI);
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#undef DECLARE_GIC_IPI
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}
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#endif /* RT_USING_SMP */
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}
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rt_err_t gic_common_configure_irq(void *base, int irq, rt_uint32_t mode, void (*sync_access)(void *), void *data)
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{
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rt_err_t err = RT_EOK;
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rt_ubase_t level;
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rt_uint32_t val, oldval;
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rt_uint32_t confoff = (irq / 16) * 4;
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rt_uint32_t confmask = 0x2 << ((irq % 16) * 2);
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static RT_DEFINE_SPINLOCK(ic_lock);
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level = rt_spin_lock_irqsave(&ic_lock);
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val = oldval = HWREG32(base + confoff);
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if (mode & RT_IRQ_MODE_LEVEL_MASK)
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{
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/* Level-sensitive */
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val &= ~confmask;
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}
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else if (mode & RT_IRQ_MODE_EDGE_BOTH)
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{
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/* Edge-triggered */
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val |= confmask;
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}
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if (val != oldval)
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{
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HWREG32(base + confoff) = val;
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if (HWREG32(base + confoff) != val)
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{
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err = -RT_EINVAL;
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}
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if (sync_access)
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{
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sync_access(data);
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}
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}
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rt_spin_unlock_irqrestore(&ic_lock, level);
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return err;
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}
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void gic_common_dist_config(void *base, int max_irqs, void (*sync_access)(void *), void *data)
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{
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rt_uint32_t i;
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/* Set all global interrupts to be level triggered, active low. */
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for (i = 32; i < max_irqs; i += 16)
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{
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HWREG32(base + GIC_DIST_CONFIG + i / 4) = GICD_INT_ACTLOW_LVLTRIG;
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}
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/* Set priority on all global interrupts. */
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for (i = 32; i < max_irqs; i += 4)
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{
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HWREG32(base + GIC_DIST_PRI + i * 4 / 4) = GICD_INT_DEF_PRI_X4;
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}
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/* Disable all SPIs. */
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for (i = 32; i < max_irqs; i += 32)
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{
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HWREG32(base + GIC_DIST_ACTIVE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
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HWREG32(base + GIC_DIST_ENABLE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
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}
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if (sync_access)
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{
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sync_access(data);
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}
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}
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void gic_common_cpu_config(void *base, int nr, void (*sync_access)(void *), void *data)
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{
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rt_uint32_t i;
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/* Disable all SGIs, PPIs. */
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for (i = 0; i < nr; i += 32)
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{
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HWREG32(base + GIC_DIST_ACTIVE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
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HWREG32(base + GIC_DIST_ENABLE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
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}
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/* Set priority on all PPI and SGI. */
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for (i = 0; i < nr; i += 4)
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{
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HWREG32(base + GIC_DIST_PRI + i * 4 / 4) = GICD_INT_DEF_PRI_X4;
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}
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if (sync_access)
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{
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sync_access(data);
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}
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}
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void gic_fill_ppi_affinity(rt_bitmap_t *affinity)
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{
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for (int cpuid = 0; cpuid < RT_CPUS_NR; ++cpuid)
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{
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RT_IRQ_AFFINITY_SET(affinity, cpuid);
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}
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}
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59
RT_Thread/components/drivers/pic/pic-gic-common.h
Normal file
59
RT_Thread/components/drivers/pic/pic-gic-common.h
Normal file
@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
|
||||
* Change Logs:
|
||||
* Date Author Notes
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* 2023-01-30 GuEe-GUI first version
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*/
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#ifndef __PIC_GIC_COMMON_H__
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#define __PIC_GIC_COMMON_H__
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#include <rtdef.h>
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#ifdef RT_PCI_MSI
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#include <drivers/pci_msi.h>
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#endif
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#include <drivers/ofw.h>
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#define GIC_SGI_NR 16
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#define GICD_INT_DEF_PRI 0xa0U
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#define GICD_INT_DEF_PRI_X4 \
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( \
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(GICD_INT_DEF_PRI << 24) | \
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(GICD_INT_DEF_PRI << 16) | \
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||||
(GICD_INT_DEF_PRI << 8) | \
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GICD_INT_DEF_PRI \
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)
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||||
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struct gic_quirk
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{
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const char *desc;
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const char *compatible;
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rt_err_t (*init)(void *data);
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||||
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rt_uint32_t iidr;
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rt_uint32_t iidr_mask;
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||||
};
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void gic_common_init_quirk_ofw(const struct rt_ofw_node *ic_np, const struct gic_quirk *quirks, void *data);
|
||||
void gic_common_init_quirk_hw(rt_uint32_t iidr, const struct gic_quirk *quirks, void *data);
|
||||
|
||||
void gic_common_sgi_config(void *base, void *data, int irq_base);
|
||||
rt_err_t gic_common_configure_irq(void *base, int irq, rt_uint32_t mode, void (*sync_access)(void *), void *data);
|
||||
void gic_common_dist_config(void *base, int max_irqs, void (*sync_access)(void *), void *data);
|
||||
void gic_common_cpu_config(void *base, int nr, void (*sync_access)(void *), void *data);
|
||||
|
||||
void gic_fill_ppi_affinity(rt_bitmap_t *affinity);
|
||||
|
||||
#ifdef RT_PIC_ARM_GIC_V2M
|
||||
rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
|
||||
#endif
|
||||
#ifdef RT_PIC_ARM_GIC_V3_ITS
|
||||
rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
|
||||
#endif
|
||||
|
||||
#endif /* __PIC_GIC_COMMON_H__ */
|
||||
666
RT_Thread/components/drivers/pic/pic-gicv2.c
Normal file
666
RT_Thread/components/drivers/pic/pic-gicv2.c
Normal file
@ -0,0 +1,666 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
* 2014-04-03 Grissiom many enhancements
|
||||
* 2018-11-22 Jesven add rt_hw_ipi_send()
|
||||
* add rt_hw_ipi_handler_install()
|
||||
* 2022-08-24 GuEe-GUI add pic support
|
||||
* 2022-11-07 GuEe-GUI add v2m support
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define DBG_TAG "pic.gicv2"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#include <cpuport.h>
|
||||
|
||||
#include <ioremap.h>
|
||||
|
||||
#include "pic-gicv2.h"
|
||||
#include "pic-gic-common.h"
|
||||
|
||||
#define GIC_CPU_IMAX 8
|
||||
|
||||
#define raw_to_gicv2(raw) rt_container_of(raw, struct gicv2, parent)
|
||||
|
||||
static rt_bool_t needs_rmw_access = RT_FALSE;
|
||||
static int _gicv2_nr = 0, _init_cpu_id = 0;
|
||||
static struct gicv2 _gicv2_list[RT_PIC_ARM_GIC_MAX_NR] = {};
|
||||
static rt_bool_t _gicv2_eoi_mode_ns = RT_FALSE;
|
||||
static rt_uint8_t _gicv2_cpumask_map[GIC_CPU_IMAX] =
|
||||
{
|
||||
[0 ... GIC_CPU_IMAX - 1] = 0xff,
|
||||
};
|
||||
|
||||
static rt_uint8_t gicv2_cpumask_map(struct gicv2 *gic)
|
||||
{
|
||||
rt_uint32_t mask, i;
|
||||
|
||||
for (i = mask = 0; i < 32; i += 4)
|
||||
{
|
||||
mask = HWREG32(gic->dist_base + GIC_DIST_TARGET + i);
|
||||
mask |= mask >> 16;
|
||||
mask |= mask >> 8;
|
||||
|
||||
if (mask)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static void gicv2_dist_init(struct gicv2 *gic)
|
||||
{
|
||||
void *base = gic->dist_base;
|
||||
rt_uint32_t i;
|
||||
rt_uint32_t cpumask = gicv2_cpumask_map(gic);
|
||||
|
||||
_init_cpu_id = rt_hw_cpu_id();
|
||||
|
||||
gic->max_irq = HWREG32(base + GIC_DIST_TYPE) & 0x1f;
|
||||
gic->max_irq = (gic->max_irq + 1) * 32;
|
||||
|
||||
/*
|
||||
* The GIC only supports up to 1020 interrupt sources.
|
||||
* Limit this to either the architected maximum, or the
|
||||
* platform maximum.
|
||||
*/
|
||||
if (gic->max_irq > 1020)
|
||||
{
|
||||
gic->max_irq = 1020;
|
||||
}
|
||||
|
||||
LOG_D("Max irq = %d", gic->max_irq);
|
||||
|
||||
if (gic->skip_init)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
HWREG32(base + GIC_DIST_CTRL) = GICD_DISABLE;
|
||||
|
||||
/* Set all global (unused) interrupts to this CPU only. */
|
||||
cpumask |= cpumask << 8;
|
||||
cpumask |= cpumask << 16;
|
||||
|
||||
for (i = 32; i < gic->max_irq; i += 4)
|
||||
{
|
||||
HWREG32(base + GIC_DIST_TARGET + i * 4 / 4) = cpumask;
|
||||
}
|
||||
|
||||
gic_common_dist_config(base, gic->max_irq, RT_NULL, RT_NULL);
|
||||
|
||||
HWREG32(base + GIC_DIST_CTRL) = GICD_ENABLE;
|
||||
}
|
||||
|
||||
static void gicv2_cpu_init(struct gicv2 *gic)
|
||||
{
|
||||
rt_uint32_t cpumask;
|
||||
void *base = gic->cpu_base;
|
||||
rt_uint32_t config = GICC_ENABLE;
|
||||
int cpu_id = rt_hw_cpu_id();
|
||||
|
||||
cpumask = gicv2_cpumask_map(gic);
|
||||
_gicv2_cpumask_map[cpu_id] = cpumask;
|
||||
|
||||
/*
|
||||
* Clear our mask from the other map entries in case they're
|
||||
* still undefined.
|
||||
*/
|
||||
for (int i = 0; i < RT_ARRAY_SIZE(_gicv2_cpumask_map); ++i)
|
||||
{
|
||||
if (i != cpu_id)
|
||||
{
|
||||
_gicv2_cpumask_map[i] &= ~cpumask;
|
||||
}
|
||||
}
|
||||
|
||||
gic_common_cpu_config(gic->dist_base, 32, RT_NULL, RT_NULL);
|
||||
|
||||
HWREG32(base + GIC_CPU_PRIMASK) = GICC_INT_PRI_THRESHOLD;
|
||||
HWREG32(base + GIC_CPU_BINPOINT) = 0x7;
|
||||
|
||||
#ifdef ARCH_SUPPORT_HYP
|
||||
_gicv2_eoi_mode_ns = RT_TRUE;
|
||||
#else
|
||||
_gicv2_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv2_eoimode", 0);
|
||||
#endif
|
||||
|
||||
if (_gicv2_eoi_mode_ns)
|
||||
{
|
||||
config |= GIC_CPU_CTRL_EOI_MODE_NS;
|
||||
}
|
||||
|
||||
HWREG32(base + GIC_CPU_CTRL) = config;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_init(struct rt_pic *pic)
|
||||
{
|
||||
gicv2_cpu_init(rt_container_of(pic, struct gicv2, parent));
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void gicv2_irq_ack(struct rt_pic_irq *pirq)
|
||||
{
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
if (!_gicv2_eoi_mode_ns)
|
||||
{
|
||||
HWREG32(gic->dist_base + GIC_DIST_PENDING_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
|
||||
}
|
||||
|
||||
HWREG32(gic->cpu_base + GIC_CPU_EOI) = hwirq;
|
||||
}
|
||||
|
||||
static void gicv2_irq_mask(struct rt_pic_irq *pirq)
|
||||
{
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
HWREG32(gic->dist_base + GIC_DIST_ENABLE_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
|
||||
}
|
||||
|
||||
static void gicv2_irq_unmask(struct rt_pic_irq *pirq)
|
||||
{
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
HWREG32(gic->dist_base + GIC_DIST_ENABLE_SET + hwirq / 32 * 4) = 1U << (hwirq % 32);
|
||||
}
|
||||
|
||||
static void gicv2_irq_eoi(struct rt_pic_irq *pirq)
|
||||
{
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
if (_gicv2_eoi_mode_ns)
|
||||
{
|
||||
HWREG32(gic->cpu_base + GIC_CPU_DIR) = pirq->hwirq;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
|
||||
{
|
||||
rt_uint32_t mask;
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
mask = HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4);
|
||||
mask &= ~(0xffU << ((hwirq % 4) * 8));
|
||||
mask |= ((priority & 0xffU) << ((hwirq % 4) * 8));
|
||||
HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4) = mask;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
|
||||
{
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
rt_uint32_t target_list = ((rt_uint8_t *)affinity)[gic - &_gicv2_list[0]];
|
||||
rt_uint8_t valb = _gicv2_cpumask_map[__rt_ffs(target_list) - 1];
|
||||
void *io_addr = gic->dist_base + GIC_DIST_TARGET + hwirq;
|
||||
|
||||
if (valb == 0xfe)
|
||||
{
|
||||
return -RT_EIO;
|
||||
}
|
||||
|
||||
if (needs_rmw_access)
|
||||
{
|
||||
/* RMW write byte */
|
||||
rt_uint32_t val;
|
||||
rt_ubase_t level;
|
||||
rt_ubase_t offset = (rt_ubase_t)io_addr & 3UL, shift = offset * 8;
|
||||
static RT_DEFINE_SPINLOCK(rmw_lock);
|
||||
|
||||
level = rt_spin_lock_irqsave(&rmw_lock);
|
||||
|
||||
io_addr -= offset;
|
||||
val = HWREG32(io_addr);
|
||||
val &= ~RT_GENMASK(shift + 7, shift);
|
||||
val |= valb << shift;
|
||||
HWREG32(io_addr) = val;
|
||||
|
||||
rt_spin_unlock_irqrestore(&rmw_lock, level);
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREG8(io_addr) = valb;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
int hwirq = pirq->hwirq;
|
||||
struct gicv2 *gic = raw_to_gicv2(pirq->pic);
|
||||
|
||||
if (hwirq >= GIC_SGI_NR)
|
||||
{
|
||||
err = gic_common_configure_irq(gic->dist_base + GIC_DIST_CONFIG, pirq->hwirq, mode, RT_NULL, RT_NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
err = -RT_ENOSYS;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void gicv2_irq_send_ipi(struct rt_pic_irq *pirq, rt_bitmap_t *cpumask)
|
||||
{
|
||||
struct gicv2 *gic;
|
||||
int sgi = pirq->hwirq;
|
||||
rt_uint8_t *target_list = (rt_uint8_t *)cpumask;
|
||||
|
||||
for (int i = 0; i < _gicv2_nr; ++i)
|
||||
{
|
||||
if (*target_list)
|
||||
{
|
||||
gic = &_gicv2_list[i];
|
||||
|
||||
HWREG32(gic->dist_base + GIC_DIST_SOFTINT) = ((*target_list & 0xffU) << 16) | (sgi & 0xf);
|
||||
|
||||
rt_hw_dsb();
|
||||
}
|
||||
|
||||
++target_list;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
rt_uint32_t offset = 0;
|
||||
struct gicv2 *gic = raw_to_gicv2(pic);
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case RT_IRQ_STATE_PENDING:
|
||||
offset = state ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
|
||||
break;
|
||||
case RT_IRQ_STATE_ACTIVE:
|
||||
offset = state ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
|
||||
break;
|
||||
case RT_IRQ_STATE_MASKED:
|
||||
offset = state ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
|
||||
break;
|
||||
default:
|
||||
err = -RT_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!err)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (hwirq % 32);
|
||||
|
||||
HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) = mask;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
rt_uint32_t offset = 0;
|
||||
struct gicv2 *gic = raw_to_gicv2(pic);
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case RT_IRQ_STATE_PENDING:
|
||||
offset = GIC_DIST_PENDING_SET;
|
||||
break;
|
||||
case RT_IRQ_STATE_ACTIVE:
|
||||
offset = GIC_DIST_ACTIVE_SET;
|
||||
break;
|
||||
case RT_IRQ_STATE_MASKED:
|
||||
offset = GIC_DIST_ENABLE_SET;
|
||||
break;
|
||||
default:
|
||||
err = -RT_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!err)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (hwirq % 32);
|
||||
|
||||
*out_state = !!(HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) & mask);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int gicv2_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode)
|
||||
{
|
||||
int irq, irq_index = hwirq - GIC_SGI_NR;
|
||||
struct rt_pic_irq *pirq = rt_pic_find_irq(pic, irq_index);
|
||||
|
||||
if (pirq && hwirq >= GIC_SGI_NR)
|
||||
{
|
||||
pirq->mode = mode;
|
||||
pirq->priority = GICD_INT_DEF_PRI;
|
||||
|
||||
if (hwirq < 32)
|
||||
{
|
||||
gic_fill_ppi_affinity(pirq->affinity);
|
||||
}
|
||||
else
|
||||
{
|
||||
RT_IRQ_AFFINITY_SET(pirq->affinity, _init_cpu_id);
|
||||
}
|
||||
|
||||
irq = rt_pic_config_irq(pic, irq_index, hwirq);
|
||||
|
||||
if (irq >= 0 && mode != RT_IRQ_MODE_LEVEL_HIGH)
|
||||
{
|
||||
gicv2_irq_set_triger_mode(pirq, mode);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
irq = -1;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_irq_parse(struct rt_pic *pic, struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
|
||||
if (args->args_count == 3)
|
||||
{
|
||||
out_pirq->mode = args->args[2] & RT_IRQ_MODE_MASK;
|
||||
|
||||
switch (args->args[0])
|
||||
{
|
||||
case 0:
|
||||
/* SPI */
|
||||
out_pirq->hwirq = args->args[1] + 32;
|
||||
break;
|
||||
case 1:
|
||||
/* PPI */
|
||||
out_pirq->hwirq = args->args[1] + 16;
|
||||
break;
|
||||
default:
|
||||
err = -RT_ENOSYS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = -RT_EINVAL;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
const static struct rt_pic_ops gicv2_ops =
|
||||
{
|
||||
.name = "GICv2",
|
||||
.irq_init = gicv2_irq_init,
|
||||
.irq_ack = gicv2_irq_ack,
|
||||
.irq_mask = gicv2_irq_mask,
|
||||
.irq_unmask = gicv2_irq_unmask,
|
||||
.irq_eoi = gicv2_irq_eoi,
|
||||
.irq_set_priority = gicv2_irq_set_priority,
|
||||
.irq_set_affinity = gicv2_irq_set_affinity,
|
||||
.irq_set_triger_mode = gicv2_irq_set_triger_mode,
|
||||
.irq_send_ipi = gicv2_irq_send_ipi,
|
||||
.irq_set_state = gicv2_irq_set_state,
|
||||
.irq_get_state = gicv2_irq_get_state,
|
||||
.irq_map = gicv2_irq_map,
|
||||
.irq_parse = gicv2_irq_parse,
|
||||
};
|
||||
|
||||
static rt_bool_t gicv2_handler(void *data)
|
||||
{
|
||||
rt_bool_t res = RT_FALSE;
|
||||
int hwirq;
|
||||
struct gicv2 *gic = data;
|
||||
|
||||
hwirq = HWREG32(gic->cpu_base + GIC_CPU_INTACK) & 0x3ffUL;
|
||||
|
||||
if (!(hwirq >= 1020 && hwirq <= 1023))
|
||||
{
|
||||
struct rt_pic_irq *pirq;
|
||||
|
||||
if (hwirq < GIC_SGI_NR)
|
||||
{
|
||||
rt_hw_rmb();
|
||||
|
||||
pirq = rt_pic_find_ipi(&gic->parent, hwirq);
|
||||
}
|
||||
else
|
||||
{
|
||||
pirq = rt_pic_find_irq(&gic->parent, hwirq - GIC_SGI_NR);
|
||||
}
|
||||
|
||||
gicv2_irq_ack(pirq);
|
||||
|
||||
rt_pic_handle_isr(pirq);
|
||||
|
||||
gicv2_irq_eoi(pirq);
|
||||
|
||||
res = RT_TRUE;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_enable_rmw_access(void *data)
|
||||
{
|
||||
if (rt_ofw_machine_is_compatible("renesas,emev2"))
|
||||
{
|
||||
needs_rmw_access = RT_TRUE;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
static const struct gic_quirk _gicv2_quirks[] =
|
||||
{
|
||||
{
|
||||
.desc = "GICv2: Broken byte access",
|
||||
.compatible = "arm,pl390",
|
||||
.init = gicv2_enable_rmw_access,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static rt_err_t gicv2_iomap_init(struct gicv2 *gic, rt_uint64_t *regs)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
int idx;
|
||||
const char *name[] =
|
||||
{
|
||||
"Distributor",
|
||||
"CPU interfaces",
|
||||
"Virtual interface control",
|
||||
"Virtual CPU interface",
|
||||
};
|
||||
|
||||
do {
|
||||
/* GICD->GICC->GICH->GICV */
|
||||
gic->dist_size = regs[1];
|
||||
gic->dist_base = rt_ioremap((void *)regs[0], gic->dist_size);
|
||||
if (!gic->dist_base)
|
||||
{
|
||||
idx = 0;
|
||||
err = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
gic->cpu_size = regs[3];
|
||||
gic->cpu_base = rt_ioremap((void *)regs[2], gic->cpu_size);
|
||||
if (!gic->cpu_base)
|
||||
{
|
||||
idx = 1;
|
||||
err = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
/* ArchRev[4:7] */
|
||||
gic->version = HWREG32(gic->dist_base + GIC_DIST_ICPIDR2) >> 4;
|
||||
|
||||
#ifdef ARCH_SUPPORT_HYP
|
||||
if (gic->version == 1)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
gic->hyp_size = regs[5];
|
||||
gic->hyp_base = rt_ioremap((void *)regs[4], gic->hyp_size);
|
||||
if (!gic->hyp_base)
|
||||
{
|
||||
idx = 2;
|
||||
err = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
gic->vcpu_size = regs[7];
|
||||
gic->vcpu_base = rt_ioremap((void *)regs[6], gic->vcpu_size);
|
||||
if (!gic->vcpu_base)
|
||||
{
|
||||
idx = 3;
|
||||
err = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
#endif /* ARCH_SUPPORT_HYP */
|
||||
} while (0);
|
||||
|
||||
if (err)
|
||||
{
|
||||
RT_UNUSED(idx);
|
||||
RT_UNUSED(name);
|
||||
|
||||
LOG_E("gic[%d] %s IO[%p, %p] map fail", _gicv2_nr, name[idx], regs[idx * 2], regs[idx * 2 + 1]);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void gicv2_init(struct gicv2 *gic)
|
||||
{
|
||||
gicv2_dist_init(gic);
|
||||
|
||||
gic->parent.priv_data = gic;
|
||||
gic->parent.ops = &gicv2_ops;
|
||||
|
||||
rt_pic_linear_irq(&gic->parent, gic->max_irq + 1 - GIC_SGI_NR);
|
||||
gic_common_sgi_config(gic->dist_base, &gic->parent, _gicv2_nr * GIC_SGI_NR);
|
||||
|
||||
rt_pic_add_traps(gicv2_handler, gic);
|
||||
|
||||
rt_pic_user_extends(&gic->parent);
|
||||
}
|
||||
|
||||
static void gicv2_init_fail(struct gicv2 *gic)
|
||||
{
|
||||
if (gic->dist_base)
|
||||
{
|
||||
rt_iounmap(gic->dist_base);
|
||||
}
|
||||
if (gic->cpu_base)
|
||||
{
|
||||
rt_iounmap(gic->cpu_base);
|
||||
}
|
||||
if (gic->hyp_base)
|
||||
{
|
||||
rt_iounmap(gic->hyp_base);
|
||||
}
|
||||
if (gic->vcpu_base)
|
||||
{
|
||||
rt_iounmap(gic->vcpu_base);
|
||||
}
|
||||
rt_memset(gic, 0, sizeof(*gic));
|
||||
}
|
||||
|
||||
static rt_err_t gicv2_ofw_init(struct rt_ofw_node *np, const struct rt_ofw_node_id *id)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
struct gicv2 *gic = RT_NULL;
|
||||
|
||||
do {
|
||||
rt_uint64_t regs[8];
|
||||
|
||||
if (_gicv2_nr >= RT_PIC_ARM_GIC_MAX_NR)
|
||||
{
|
||||
LOG_W("GICv2/v1 table is full");
|
||||
err = -RT_EFULL;
|
||||
break;
|
||||
}
|
||||
|
||||
gic = &_gicv2_list[_gicv2_nr];
|
||||
|
||||
rt_ofw_get_address_array(np, RT_ARRAY_SIZE(regs), regs);
|
||||
|
||||
if ((err = gicv2_iomap_init(gic, regs)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if (gic->version != 1 && gic->version != 2)
|
||||
{
|
||||
LOG_E("Version = %d is not support", gic->version);
|
||||
err = -RT_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
gic->skip_init = rt_ofw_prop_read_bool(np, "skip-init");
|
||||
|
||||
gic_common_init_quirk_ofw(np, _gicv2_quirks, gic);
|
||||
gicv2_init(gic);
|
||||
|
||||
rt_ofw_data(np) = &gic->parent;
|
||||
|
||||
if (gic->version == 2)
|
||||
{
|
||||
#ifdef RT_PIC_ARM_GIC_V2M
|
||||
gicv2m_ofw_probe(np, id);
|
||||
#endif
|
||||
}
|
||||
|
||||
++_gicv2_nr;
|
||||
} while (0);
|
||||
|
||||
if (err && gic)
|
||||
{
|
||||
gicv2_init_fail(gic);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct rt_ofw_node_id gicv2_ofw_ids[] =
|
||||
{
|
||||
{ .compatible = "arm,gic-400" },
|
||||
{ .compatible = "arm,arm11mp-gic" },
|
||||
{ .compatible = "arm,arm1176jzf-devchip-gic" },
|
||||
{ .compatible = "arm,cortex-a15-gic" },
|
||||
{ .compatible = "arm,cortex-a9-gic" },
|
||||
{ .compatible = "arm,cortex-a7-gic" },
|
||||
{ .compatible = "qcom,msm-8660-qgic" },
|
||||
{ .compatible = "qcom,msm-qgic2" },
|
||||
{ .compatible = "arm,pl390" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
RT_PIC_OFW_DECLARE(gicv2, gicv2_ofw_ids, gicv2_ofw_init);
|
||||
85
RT_Thread/components/drivers/pic/pic-gicv2.h
Normal file
85
RT_Thread/components/drivers/pic/pic-gicv2.h
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
* 2023-02-01 GuEe-GUI move macros to header
|
||||
*/
|
||||
|
||||
#ifndef __PIC_GICV2_H__
|
||||
#define __PIC_GICV2_H__
|
||||
|
||||
#include <rtdef.h>
|
||||
|
||||
#include <drivers/pic.h>
|
||||
|
||||
#define GIC_DIST_CTRL 0x000
|
||||
#define GIC_DIST_TYPE 0x004
|
||||
#define GIC_DIST_IIDR 0x008
|
||||
#define GIC_DIST_IGROUP 0x080
|
||||
#define GIC_DIST_ENABLE_SET 0x100
|
||||
#define GIC_DIST_ENABLE_CLEAR 0x180
|
||||
#define GIC_DIST_PENDING_SET 0x200
|
||||
#define GIC_DIST_PENDING_CLEAR 0x280
|
||||
#define GIC_DIST_ACTIVE_SET 0x300
|
||||
#define GIC_DIST_ACTIVE_CLEAR 0x380
|
||||
#define GIC_DIST_PRI 0x400
|
||||
#define GIC_DIST_TARGET 0x800
|
||||
#define GIC_DIST_CONFIG 0xc00
|
||||
#define GIC_DIST_SOFTINT 0xf00
|
||||
#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
|
||||
#define GIC_DIST_SGI_PENDING_SET 0xf20
|
||||
#define GIC_DIST_ICPIDR2 0xfe8
|
||||
|
||||
#define GICD_ENABLE 0x1
|
||||
#define GICD_DISABLE 0x0
|
||||
#define GICD_INT_ACTLOW_LVLTRIG 0x0
|
||||
#define GICD_INT_EN_CLR_X32 0xffffffff
|
||||
#define GICD_INT_EN_SET_SGI 0x0000ffff
|
||||
#define GICD_INT_EN_CLR_PPI 0xffff0000
|
||||
|
||||
#define GICD_GROUP0 0
|
||||
#define GICD_GROUP1 (~GICD_GROUP0)
|
||||
|
||||
#define GIC_CPU_CTRL 0x00
|
||||
#define GIC_CPU_PRIMASK 0x04
|
||||
#define GIC_CPU_BINPOINT 0x08
|
||||
#define GIC_CPU_INTACK 0x0c
|
||||
#define GIC_CPU_EOI 0x10
|
||||
#define GIC_CPU_RUNNINGPRI 0x14
|
||||
#define GIC_CPU_HIGHPRI 0x18
|
||||
#define GIC_CPU_ALIAS_BINPOINT 0x1c
|
||||
#define GIC_CPU_ACTIVEPRIO 0xd0
|
||||
#define GIC_CPU_IIDR 0xfc
|
||||
#define GIC_CPU_DIR 0x1000
|
||||
|
||||
#define GICC_ENABLE 0x1
|
||||
#define GICC_INT_PRI_THRESHOLD 0xf0 /* priority levels 16 */
|
||||
#define GIC_CPU_CTRL_ENABLE_GRP0 (1 << 0)
|
||||
#define GIC_CPU_CTRL_ENABLE_GRP1 (1 << 1)
|
||||
#define GIC_CPU_CTRL_EOI_MODE_NS (1 << 9)
|
||||
|
||||
struct gicv2
|
||||
{
|
||||
struct rt_pic parent;
|
||||
|
||||
int version;
|
||||
int max_irq;
|
||||
|
||||
void *dist_base;
|
||||
rt_size_t dist_size;
|
||||
void *cpu_base;
|
||||
rt_size_t cpu_size;
|
||||
|
||||
void *hyp_base;
|
||||
rt_size_t hyp_size;
|
||||
void *vcpu_base;
|
||||
rt_size_t vcpu_size;
|
||||
|
||||
rt_bool_t skip_init;
|
||||
};
|
||||
|
||||
#endif /* __IRQ_GICV2_H__ */
|
||||
378
RT_Thread/components/drivers/pic/pic-gicv2m.c
Normal file
378
RT_Thread/components/drivers/pic/pic-gicv2m.c
Normal file
@ -0,0 +1,378 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-11-07 GuEe-GUI first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define DBG_TAG "pic.gicv2m"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#include <mmu.h>
|
||||
#include <cpuport.h>
|
||||
#include "pic-gic-common.h"
|
||||
|
||||
/*
|
||||
* MSI_TYPER:
|
||||
* [31:26] Reserved
|
||||
* [25:16] lowest SPI assigned to MSI
|
||||
* [15:10] Reserved
|
||||
* [9:0] Numer of SPIs assigned to MSI
|
||||
*/
|
||||
#define V2M_MSI_TYPER 0x008
|
||||
#define V2M_MSI_TYPER_BASE_SHIFT 16
|
||||
#define V2M_MSI_TYPER_BASE_MASK 0x3ff
|
||||
#define V2M_MSI_TYPER_NUM_MASK 0x3ff
|
||||
#define V2M_MSI_SETSPI_NS 0x040
|
||||
#define V2M_MIN_SPI 32
|
||||
#define V2M_MAX_SPI 1019
|
||||
#define V2M_MSI_IIDR 0xfcc
|
||||
|
||||
#define V2M_MSI_TYPER_BASE_SPI(x) (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
|
||||
#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
|
||||
|
||||
/* APM X-Gene with GICv2m MSI_IIDR register value */
|
||||
#define XGENE_GICV2M_MSI_IIDR 0x06000170
|
||||
/* Broadcom NS2 GICv2m MSI_IIDR register value */
|
||||
#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
|
||||
|
||||
/* List of flags for specific v2m implementation */
|
||||
#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
|
||||
#define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002
|
||||
|
||||
struct gicv2m
|
||||
{
|
||||
struct rt_pic parent;
|
||||
|
||||
void *base;
|
||||
void *base_phy;
|
||||
rt_uint32_t spi_start; /* The SPI number that MSIs start */
|
||||
rt_uint32_t spis_nr; /* The number of SPIs for MSIs */
|
||||
rt_uint32_t spi_offset; /* Offset to be subtracted from SPI number */
|
||||
|
||||
rt_bitmap_t *vectors; /* MSI vector bitmap */
|
||||
rt_uint32_t flags; /* Flags for v2m's specific implementation */
|
||||
|
||||
void *gic;
|
||||
struct rt_spinlock lock;
|
||||
};
|
||||
|
||||
#define raw_to_gicv2m(raw) rt_container_of(raw, struct gicv2m, parent)
|
||||
|
||||
static rt_ubase_t gicv2m_get_msi_addr(struct gicv2m *v2m, int hwirq)
|
||||
{
|
||||
rt_ubase_t addr;
|
||||
|
||||
if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
|
||||
{
|
||||
addr = (rt_ubase_t)v2m->base_phy | ((hwirq - 32) << 3);
|
||||
}
|
||||
else
|
||||
{
|
||||
addr = (rt_ubase_t)v2m->base_phy + V2M_MSI_SETSPI_NS;
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static rt_bool_t is_msi_spi_valid(rt_uint32_t base, rt_uint32_t num)
|
||||
{
|
||||
if (base < V2M_MIN_SPI)
|
||||
{
|
||||
LOG_E("Invalid MSI base SPI (base: %u)", base);
|
||||
|
||||
return RT_FALSE;
|
||||
}
|
||||
else if ((num == 0) || (base + num > V2M_MAX_SPI))
|
||||
{
|
||||
LOG_E("Number of SPIs (%u) exceed maximum (%u)", num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
|
||||
|
||||
return RT_FALSE;
|
||||
}
|
||||
|
||||
return RT_TRUE;
|
||||
}
|
||||
|
||||
static void gicv2m_irq_mask(struct rt_pic_irq *pirq)
|
||||
{
|
||||
rt_pci_msi_mask_irq(pirq);
|
||||
rt_pic_irq_parent_mask(pirq);
|
||||
}
|
||||
|
||||
static void gicv2m_irq_unmask(struct rt_pic_irq *pirq)
|
||||
{
|
||||
rt_pci_msi_unmask_irq(pirq);
|
||||
rt_pic_irq_parent_unmask(pirq);
|
||||
}
|
||||
|
||||
static void gicv2m_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg)
|
||||
{
|
||||
rt_ubase_t addr;
|
||||
struct gicv2m *v2m = raw_to_gicv2m(pirq->pic);
|
||||
|
||||
addr = gicv2m_get_msi_addr(v2m, pirq->hwirq);
|
||||
|
||||
msg->address_hi = rt_upper_32_bits(addr);
|
||||
msg->address_lo = rt_lower_32_bits(addr);
|
||||
|
||||
if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
|
||||
{
|
||||
msg->data = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
msg->data = pirq->hwirq;
|
||||
}
|
||||
|
||||
if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
|
||||
{
|
||||
msg->data -= v2m->spi_offset;
|
||||
}
|
||||
}
|
||||
|
||||
static int gicv2m_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc)
|
||||
{
|
||||
rt_ubase_t level;
|
||||
int irq, parent_irq, hwirq, hwirq_index;
|
||||
struct rt_pic_irq *pirq;
|
||||
struct gicv2m *v2m = raw_to_gicv2m(pic);
|
||||
struct rt_pic *ppic = v2m->gic;
|
||||
|
||||
level = rt_spin_lock_irqsave(&v2m->lock);
|
||||
hwirq_index = rt_bitmap_next_clear_bit(v2m->vectors, 0, v2m->spis_nr);
|
||||
|
||||
if (hwirq_index >= v2m->spis_nr)
|
||||
{
|
||||
irq = -RT_EEMPTY;
|
||||
goto _out_lock;
|
||||
}
|
||||
|
||||
hwirq = v2m->spi_start + v2m->spi_offset + hwirq_index;
|
||||
|
||||
parent_irq = ppic->ops->irq_map(ppic, hwirq, RT_IRQ_MODE_EDGE_RISING);
|
||||
if (parent_irq < 0)
|
||||
{
|
||||
irq = parent_irq;
|
||||
goto _out_lock;
|
||||
}
|
||||
|
||||
irq = rt_pic_config_irq(pic, hwirq_index, hwirq);
|
||||
if (irq < 0)
|
||||
{
|
||||
goto _out_lock;
|
||||
}
|
||||
pirq = rt_pic_find_irq(pic, hwirq_index);
|
||||
|
||||
pirq->mode = RT_IRQ_MODE_EDGE_RISING;
|
||||
rt_pic_cascade(pirq, parent_irq);
|
||||
|
||||
rt_bitmap_set_bit(v2m->vectors, hwirq_index);
|
||||
|
||||
_out_lock:
|
||||
rt_spin_unlock_irqrestore(&v2m->lock, level);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
static void gicv2m_irq_free_msi(struct rt_pic *pic, int irq)
|
||||
{
|
||||
rt_ubase_t level;
|
||||
struct rt_pic_irq *pirq;
|
||||
struct gicv2m *v2m = raw_to_gicv2m(pic);
|
||||
|
||||
pirq = rt_pic_find_pirq(pic, irq);
|
||||
|
||||
if (!pirq)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
rt_pic_uncascade(pirq);
|
||||
|
||||
level = rt_spin_lock_irqsave(&v2m->lock);
|
||||
rt_bitmap_clear_bit(v2m->vectors, pirq->hwirq - (v2m->spi_start + v2m->spi_offset));
|
||||
rt_spin_unlock_irqrestore(&v2m->lock, level);
|
||||
}
|
||||
|
||||
static rt_err_t gicv2m_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
|
||||
{
|
||||
struct gicv2m *v2m = raw_to_gicv2m(pic);
|
||||
struct rt_pic *ppic = v2m->gic;
|
||||
|
||||
return ppic->ops->irq_set_state(ppic, hwirq, type, state);
|
||||
}
|
||||
|
||||
static rt_err_t gicv2m_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
|
||||
{
|
||||
struct gicv2m *v2m = raw_to_gicv2m(pic);
|
||||
struct rt_pic *ppic = v2m->gic;
|
||||
|
||||
return ppic->ops->irq_get_state(ppic, hwirq, type, out_state);
|
||||
}
|
||||
|
||||
const static struct rt_pic_ops gicv2m_ops =
|
||||
{
|
||||
.name = "GICv2m",
|
||||
.irq_ack = rt_pic_irq_parent_ack,
|
||||
.irq_mask = gicv2m_irq_mask,
|
||||
.irq_unmask = gicv2m_irq_unmask,
|
||||
.irq_eoi = rt_pic_irq_parent_eoi,
|
||||
.irq_set_priority = rt_pic_irq_parent_set_priority,
|
||||
.irq_set_affinity = rt_pic_irq_parent_set_affinity,
|
||||
.irq_compose_msi_msg = gicv2m_compose_msi_msg,
|
||||
.irq_alloc_msi = gicv2m_irq_alloc_msi,
|
||||
.irq_free_msi = gicv2m_irq_free_msi,
|
||||
.irq_set_state = gicv2m_irq_set_state,
|
||||
.irq_get_state = gicv2m_irq_get_state,
|
||||
.flags = RT_PIC_F_IRQ_ROUTING,
|
||||
};
|
||||
|
||||
static const struct rt_ofw_node_id gicv2m_ofw_match[] =
|
||||
{
|
||||
{ .compatible = "arm,gic-v2m-frame" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *np, const struct rt_ofw_node_id *id)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
struct rt_ofw_node *v2m_np;
|
||||
|
||||
rt_ofw_foreach_available_child_node(np, v2m_np)
|
||||
{
|
||||
struct gicv2m *v2m;
|
||||
rt_size_t bitmap_size;
|
||||
rt_uint32_t spi_start = 0, spis_nr = 0;
|
||||
|
||||
if (!rt_ofw_node_match(v2m_np, gicv2m_ofw_match))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!rt_ofw_prop_read_bool(v2m_np, "msi-controller"))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(v2m = rt_malloc(sizeof(*v2m))))
|
||||
{
|
||||
rt_ofw_node_put(v2m_np);
|
||||
|
||||
err = -RT_ENOMEM;
|
||||
break;
|
||||
}
|
||||
|
||||
v2m->base = rt_ofw_iomap(v2m_np, 0);
|
||||
|
||||
if (!v2m->base)
|
||||
{
|
||||
LOG_E("%s: IO map failed", rt_ofw_node_full_name(v2m_np));
|
||||
continue;
|
||||
}
|
||||
|
||||
v2m->base_phy = rt_kmem_v2p(v2m->base);
|
||||
v2m->flags = 0;
|
||||
|
||||
if (!rt_ofw_prop_read_u32(v2m_np, "arm,msi-base-spi", &spi_start) &&
|
||||
!rt_ofw_prop_read_u32(v2m_np, "arm,msi-num-spis", &spis_nr))
|
||||
{
|
||||
LOG_I("DT overriding V2M MSI_TYPER (base:%u, num:%u)", spi_start, spis_nr);
|
||||
}
|
||||
|
||||
if (spi_start && spis_nr)
|
||||
{
|
||||
v2m->spi_start = spi_start;
|
||||
v2m->spis_nr = spis_nr;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_uint32_t typer;
|
||||
|
||||
/* Graviton should always have explicit spi_start/spis_nr */
|
||||
if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
|
||||
{
|
||||
goto _fail;
|
||||
}
|
||||
typer = HWREG32(v2m->base + V2M_MSI_TYPER);
|
||||
|
||||
v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
|
||||
v2m->spis_nr = V2M_MSI_TYPER_NUM_SPI(typer);
|
||||
}
|
||||
|
||||
if (!is_msi_spi_valid(v2m->spi_start, v2m->spis_nr))
|
||||
{
|
||||
goto _fail;
|
||||
}
|
||||
|
||||
/*
|
||||
* APM X-Gene GICv2m implementation has an erratum where
|
||||
* the MSI data needs to be the offset from the spi_start
|
||||
* in order to trigger the correct MSI interrupt. This is
|
||||
* different from the standard GICv2m implementation where
|
||||
* the MSI data is the absolute value within the range from
|
||||
* spi_start to (spi_start + num_spis).
|
||||
*
|
||||
* Broadcom NS2 GICv2m implementation has an erratum where the MSI data
|
||||
* is 'spi_number - 32'
|
||||
*
|
||||
* Reading that register fails on the Graviton implementation
|
||||
*/
|
||||
if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY))
|
||||
{
|
||||
switch (HWREG32(v2m->base + V2M_MSI_IIDR))
|
||||
{
|
||||
case XGENE_GICV2M_MSI_IIDR:
|
||||
v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
|
||||
v2m->spi_offset = v2m->spi_start;
|
||||
break;
|
||||
|
||||
case BCM_NS2_GICV2M_MSI_IIDR:
|
||||
v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
|
||||
v2m->spi_offset = 32;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bitmap_size = RT_BITMAP_LEN(v2m->spis_nr) * sizeof(rt_bitmap_t);
|
||||
|
||||
if (!(v2m->vectors = rt_calloc(1, bitmap_size)))
|
||||
{
|
||||
err = -RT_ENOMEM;
|
||||
goto _fail;
|
||||
}
|
||||
|
||||
rt_spin_lock_init(&v2m->lock);
|
||||
|
||||
v2m->parent.priv_data = v2m;
|
||||
v2m->parent.ops = &gicv2m_ops;
|
||||
v2m->gic = rt_ofw_data(np);
|
||||
|
||||
rt_pic_linear_irq(&v2m->parent, v2m->spis_nr);
|
||||
rt_pic_user_extends(&v2m->parent);
|
||||
|
||||
rt_ofw_data(v2m_np) = &v2m->parent;
|
||||
rt_ofw_node_set_flag(v2m_np, RT_OFW_F_READLY);
|
||||
|
||||
continue;
|
||||
|
||||
_fail:
|
||||
rt_iounmap(v2m->base);
|
||||
rt_free(v2m);
|
||||
|
||||
if (err)
|
||||
{
|
||||
rt_ofw_node_put(v2m_np);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
1585
RT_Thread/components/drivers/pic/pic-gicv3-its.c
Normal file
1585
RT_Thread/components/drivers/pic/pic-gicv3-its.c
Normal file
File diff suppressed because it is too large
Load Diff
1105
RT_Thread/components/drivers/pic/pic-gicv3.c
Normal file
1105
RT_Thread/components/drivers/pic/pic-gicv3.c
Normal file
File diff suppressed because it is too large
Load Diff
392
RT_Thread/components/drivers/pic/pic-gicv3.h
Normal file
392
RT_Thread/components/drivers/pic/pic-gicv3.h
Normal file
@ -0,0 +1,392 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
* 2014-04-03 Grissiom many enhancements
|
||||
* 2018-11-22 Jesven add rt_hw_ipi_send()
|
||||
* add rt_hw_ipi_handler_install()
|
||||
* 2023-02-01 GuEe-GUI move macros to header
|
||||
*/
|
||||
|
||||
#ifndef __PIC_GICV3_H__
|
||||
#define __PIC_GICV3_H__
|
||||
|
||||
#include <rtdef.h>
|
||||
|
||||
#include <cpuport.h>
|
||||
|
||||
#include <drivers/pic.h>
|
||||
#include <drivers/core/dm.h>
|
||||
#include <dt-bindings/size.h>
|
||||
|
||||
/* Distributor registers */
|
||||
#define GICD_CTLR 0x0000
|
||||
#define GICD_TYPER 0x0004
|
||||
#define GICD_IIDR 0x0008
|
||||
#define GICD_TYPER2 0x000C
|
||||
#define GICD_STATUSR 0x0010
|
||||
#define GICD_SETSPI_NSR 0x0040
|
||||
#define GICD_CLRSPI_NSR 0x0048
|
||||
#define GICD_SETSPI_SR 0x0050
|
||||
#define GICD_CLRSPI_SR 0x0058
|
||||
#define GICD_IGROUPR 0x0080
|
||||
#define GICD_ISENABLER 0x0100
|
||||
#define GICD_ICENABLER 0x0180
|
||||
#define GICD_ISPENDR 0x0200
|
||||
#define GICD_ICPENDR 0x0280
|
||||
#define GICD_ISACTIVER 0x0300
|
||||
#define GICD_ICACTIVER 0x0380
|
||||
#define GICD_IPRIORITYR 0x0400
|
||||
#define GICD_ICFGR 0x0C00
|
||||
#define GICD_IGRPMODR 0x0D00
|
||||
#define GICD_NSACR 0x0E00
|
||||
#define GICD_IGROUPRnE 0x1000
|
||||
#define GICD_ISENABLERnE 0x1200
|
||||
#define GICD_ICENABLERnE 0x1400
|
||||
#define GICD_ISPENDRnE 0x1600
|
||||
#define GICD_ICPENDRnE 0x1800
|
||||
#define GICD_ISACTIVERnE 0x1A00
|
||||
#define GICD_ICACTIVERnE 0x1C00
|
||||
#define GICD_IPRIORITYRnE 0x2000
|
||||
#define GICD_ICFGRnE 0x3000
|
||||
#define GICD_IROUTER 0x6000
|
||||
#define GICD_IROUTERnE 0x8000
|
||||
#define GICD_IDREGS 0xFFD0
|
||||
#define GICD_PIDR2 0xFFE8
|
||||
|
||||
#define GICD_ITARGETSR 0x0800
|
||||
#define GICD_SGIR 0x0F00
|
||||
#define GICD_CPENDSGIR 0x0F10
|
||||
#define GICD_SPENDSGIR 0x0F20
|
||||
|
||||
#define GICD_CTLR_RWP (1U << 31)
|
||||
#define GICD_CTLR_nASSGIreq (1U << 8)
|
||||
#define GICD_CTLR_DS (1U << 6)
|
||||
#define GICD_CTLR_ARE_NS (1U << 4)
|
||||
#define GICD_CTLR_ENABLE_G1A (1U << 1)
|
||||
#define GICD_CTLR_ENABLE_G1 (1U << 0)
|
||||
|
||||
#define GICD_TYPER_RSS (1U << 26)
|
||||
#define GICD_TYPER_LPIS (1U << 17)
|
||||
#define GICD_TYPER_MBIS (1U << 16)
|
||||
#define GICD_TYPER_ESPI (1U << 8)
|
||||
#define GICD_TYPER_ID_BITS(t) ((((t) >> 19) & 0x1f) + 1)
|
||||
#define GICD_TYPER_NUM_LPIS(t) ((((t) >> 11) & 0x1f) + 1)
|
||||
#define GICD_TYPER_SPIS(t) ((((t) & 0x1f) + 1) * 32)
|
||||
#define GICD_TYPER_ESPIS(t) (((t) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((t) >> 27) : 0)
|
||||
|
||||
/* Redistributor registers */
|
||||
#define GICR_CTLR 0x0000
|
||||
#define GICR_IIDR 0x0004
|
||||
#define GICR_TYPER 0x0008
|
||||
#define GICR_STATUSR 0x0010
|
||||
#define GICR_WAKER 0x0014
|
||||
#define GICR_MPAMIDR 0x0018
|
||||
#define GICR_PARTIDR 0x001C
|
||||
#define GICR_SETLPIR 0x0040
|
||||
#define GICR_CLRLPIR 0x0048
|
||||
#define GICR_PROPBASER 0x0070
|
||||
#define GICR_PENDBASER 0x0078
|
||||
#define GICR_INVLPIR 0x00A0
|
||||
#define GICR_INVALLR 0x00B0
|
||||
#define GICR_SYNCR 0x00C0
|
||||
#define GICR_PIDR2 GICD_PIDR2
|
||||
|
||||
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
|
||||
#define GICR_CTLR_CES (1UL << 1)
|
||||
#define GICR_CTLR_IR (1UL << 2)
|
||||
#define GICR_CTLR_RWP (1UL << 3)
|
||||
|
||||
#define GICR_TYPER_CPU_NO(r) (((r) >> 8) & 0xffff)
|
||||
|
||||
#define GICR_RD_BASE_SIZE (64 * SIZE_KB)
|
||||
#define GICR_SGI_OFFSET (64 * SIZE_KB)
|
||||
#define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET
|
||||
|
||||
/* Re-Distributor registers, offsets from SGI_base */
|
||||
#define GICR_IGROUPR0 GICD_IGROUPR
|
||||
#define GICR_ISENABLER0 GICD_ISENABLER
|
||||
#define GICR_ICENABLER0 GICD_ICENABLER
|
||||
#define GICR_ISPENDR0 GICD_ISPENDR
|
||||
#define GICR_ICPENDR0 GICD_ICPENDR
|
||||
#define GICR_ISACTIVER0 GICD_ISACTIVER
|
||||
#define GICR_ICACTIVER0 GICD_ICACTIVER
|
||||
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
|
||||
#define GICR_ICFGR0 GICD_ICFGR
|
||||
#define GICR_IGRPMODR0 GICD_IGRPMODR
|
||||
#define GICR_NSACR GICD_NSACR
|
||||
|
||||
#define GICR_TYPER_PLPIS (1U << 0)
|
||||
#define GICR_TYPER_VLPIS (1U << 1)
|
||||
#define GICR_TYPER_DIRTY (1U << 2)
|
||||
#define GICR_TYPER_DirectLPIS (1U << 3)
|
||||
#define GICR_TYPER_LAST (1U << 4)
|
||||
#define GICR_TYPER_RVPEID (1U << 7)
|
||||
#define GICR_TYPER_COM_LPI_AFF RT_GENMASK_ULL(25, 24)
|
||||
#define GICR_TYPER_AFFINITY RT_GENMASK_ULL(63, 32)
|
||||
|
||||
#define GICR_INVLPIR_INTID RT_GENMASK_ULL(31, 0)
|
||||
#define GICR_INVLPIR_VPEID RT_GENMASK_ULL(47, 32)
|
||||
#define GICR_INVLPIR_V RT_GENMASK_ULL(63, 63)
|
||||
|
||||
#define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID
|
||||
#define GICR_INVALLR_V GICR_INVLPIR_V
|
||||
|
||||
#define GICR_VLPI_BASE_SIZE (64 * SIZE_KB)
|
||||
#define GICR_RESERVED_SIZE (64 * SIZE_KB)
|
||||
|
||||
#define GIC_V3_REDIST_SIZE 0x20000
|
||||
|
||||
#define GICR_TYPER_NR_PPIS(t) (16 + ({ int __ppinum = (((t) >> 27) & 0x1f); __ppinum <= 2 ? __ppinum : 0; }) * 32)
|
||||
|
||||
#define GICR_WAKER_ProcessorSleep (1U << 1)
|
||||
#define GICR_WAKER_ChildrenAsleep (1U << 2)
|
||||
|
||||
#define GICR_PROPBASER_IDBITS_MASK (0x1f)
|
||||
#define GICR_PROPBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 12))
|
||||
#define GICR_PENDBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 16))
|
||||
|
||||
/* ITS registers */
|
||||
#define GITS_CTLR 0x0000
|
||||
#define GITS_IIDR 0x0004
|
||||
#define GITS_TYPER 0x0008
|
||||
#define GITS_MPIDR 0x0018
|
||||
#define GITS_CBASER 0x0080
|
||||
#define GITS_CWRITER 0x0088
|
||||
#define GITS_CREADR 0x0090
|
||||
#define GITS_BASER 0x0100
|
||||
#define GITS_IDREGS_BASE 0xffd0
|
||||
#define GITS_PIDR0 0xffe0
|
||||
#define GITS_PIDR1 0xffe4
|
||||
#define GITS_PIDR2 GICR_PIDR2
|
||||
#define GITS_PIDR4 0xffd0
|
||||
#define GITS_CIDR0 0xfff0
|
||||
#define GITS_CIDR1 0xfff4
|
||||
#define GITS_CIDR2 0xfff8
|
||||
#define GITS_CIDR3 0xfffc
|
||||
|
||||
#define GITS_TRANSLATER 0x10040
|
||||
|
||||
#define GITS_SGIR 0x20020
|
||||
|
||||
#define GITS_SGIR_VPEID RT_GENMASK_ULL(47, 32)
|
||||
#define GITS_SGIR_VINTID RT_GENMASK_ULL(3, 0)
|
||||
|
||||
#define GITS_CTLR_ENABLE (1U << 0)
|
||||
#define GITS_CTLR_ImDe (1U << 1)
|
||||
#define GITS_CTLR_ITS_NUMBER_SHIFT 4
|
||||
#define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
|
||||
#define GITS_CTLR_QUIESCENT (1U << 31)
|
||||
|
||||
#define GITS_TYPER_PLPIS (1UL << 0)
|
||||
#define GITS_TYPER_VLPIS (1UL << 1)
|
||||
#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
|
||||
#define GITS_TYPER_ITT_ENTRY_SIZE RT_GENMASK_ULL(7, 4)
|
||||
#define GITS_TYPER_IDBITS_SHIFT 8
|
||||
#define GITS_TYPER_DEVBITS_SHIFT 13
|
||||
#define GITS_TYPER_DEVBITS RT_GENMASK_ULL(17, 13)
|
||||
#define GITS_TYPER_PTA (1UL << 19)
|
||||
#define GITS_TYPER_HCC_SHIFT 24
|
||||
#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
|
||||
#define GITS_TYPER_VMOVP (1ULL << 37)
|
||||
#define GITS_TYPER_VMAPP (1ULL << 40)
|
||||
#define GITS_TYPER_SVPET RT_GENMASK_ULL(42, 41)
|
||||
|
||||
/*
|
||||
* ITS commands
|
||||
*/
|
||||
#define GITS_CMD_MAPD 0x08
|
||||
#define GITS_CMD_MAPC 0x09
|
||||
#define GITS_CMD_MAPTI 0x0a
|
||||
#define GITS_CMD_MAPI 0x0b
|
||||
#define GITS_CMD_MOVI 0x01
|
||||
#define GITS_CMD_DISCARD 0x0f
|
||||
#define GITS_CMD_INV 0x0c
|
||||
#define GITS_CMD_MOVALL 0x0e
|
||||
#define GITS_CMD_INVALL 0x0d
|
||||
#define GITS_CMD_INT 0x03
|
||||
#define GITS_CMD_CLEAR 0x04
|
||||
#define GITS_CMD_SYNC 0x05
|
||||
|
||||
/* ITS Config Area */
|
||||
#define GITS_LPI_CFG_GROUP1 (1 << 1)
|
||||
#define GITS_LPI_CFG_ENABLED (1 << 0)
|
||||
|
||||
/* ITS Command Queue Descriptor */
|
||||
#define GITS_BASER_SHAREABILITY_SHIFT 10
|
||||
#define GITS_BASER_INNER_CACHEABILITY_SHIFT 59
|
||||
#define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53
|
||||
#define GITS_CBASER_VALID (1UL << 63)
|
||||
#define GITS_CBASER_SHAREABILITY_SHIFT 10
|
||||
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT 59
|
||||
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT 53
|
||||
#define GICR_PBASER_SHAREABILITY_SHIFT 10
|
||||
#define GICR_PBASER_INNER_CACHEABILITY_SHIFT 7
|
||||
#define GICR_PBASER_OUTER_CACHEABILITY_SHIFT 56
|
||||
|
||||
#define GITS_BASER_NR_REGS 8
|
||||
#define GITS_BASERn(idx) (GITS_BASER + sizeof(rt_uint64_t) * idx)
|
||||
|
||||
#define GITS_BASER_VALID (1ULL << 63)
|
||||
#define GITS_BASER_INDIRECT (1ULL << 62)
|
||||
#define GITS_BASER_TYPE_SHIFT 56
|
||||
#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
|
||||
#define GITS_BASER_ENTRY_SIZE_SHIFT 48
|
||||
#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
|
||||
#define GITS_BASER_PAGE_SIZE_SHIFT 8
|
||||
#define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
|
||||
#define GITS_BASER_PAGES_SHIFT 0
|
||||
|
||||
#define GITS_LVL1_ENTRY_SIZE 8UL
|
||||
|
||||
#define GITS_BASER_TYPE_NONE 0
|
||||
#define GITS_BASER_TYPE_DEVICE 1
|
||||
#define GITS_BASER_TYPE_VPE 2
|
||||
#define GITS_BASER_TYPE_RESERVED3 3
|
||||
#define GITS_BASER_TYPE_COLLECTION 4
|
||||
#define GITS_BASER_TYPE_RESERVED5 5
|
||||
#define GITS_BASER_TYPE_RESERVED6 6
|
||||
#define GITS_BASER_TYPE_RESERVED7 7
|
||||
|
||||
#define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \
|
||||
(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
|
||||
#define GITS_BASER_SHAREABILITY(reg, type) \
|
||||
(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
|
||||
|
||||
#define GIC_BASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */
|
||||
#define GIC_BASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */
|
||||
#define GIC_BASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */
|
||||
#define GIC_BASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */
|
||||
#define GIC_BASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */
|
||||
#define GIC_BASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */
|
||||
#define GIC_BASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */
|
||||
#define GIC_BASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */
|
||||
#define GIC_BASER_CACHE_MASK 0x7UL
|
||||
#define GIC_BASER_SHARE_NS 0x0UL /* Non-shareable. */
|
||||
#define GIC_BASER_SHARE_IS 0x1UL /* Inner Shareable. */
|
||||
#define GIC_BASER_SHARE_OS 0x2UL /* Outer Shareable. */
|
||||
#define GIC_BASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */
|
||||
#define GIC_BASER_SHARE_MASK 0x3UL
|
||||
|
||||
#define GITS_BASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_IS)
|
||||
#define GITS_BASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_MASK)
|
||||
#define GITS_BASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
|
||||
#define GITS_BASER_nCnB GITS_BASER_CACHEABILITY(GITS_BASER, INNER, DnGnRnE)
|
||||
#define GITS_BASER_nC GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIN)
|
||||
#define GITS_BASER_RaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWT)
|
||||
#define GITS_BASER_RaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWB)
|
||||
#define GITS_BASER_WaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWT)
|
||||
#define GITS_BASER_WaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWB)
|
||||
#define GITS_BASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWT)
|
||||
#define GITS_BASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWB)
|
||||
|
||||
#define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS)
|
||||
#define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK)
|
||||
#define GITS_CBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
|
||||
#define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE)
|
||||
#define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN)
|
||||
#define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT)
|
||||
#define GITS_CBASER_RaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWB)
|
||||
#define GITS_CBASER_WaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWT)
|
||||
#define GITS_CBASER_WaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWB)
|
||||
#define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT)
|
||||
#define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB)
|
||||
|
||||
#define GICR_PBASER_InnerShareable GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_IS)
|
||||
#define GICR_PBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_MASK)
|
||||
#define GICR_PBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, MASK)
|
||||
#define GICR_PBASER_nCnB GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, DnGnRnE)
|
||||
#define GICR_PBASER_nC GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIN)
|
||||
#define GICR_PBASER_RaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWT)
|
||||
#define GICR_PBASER_RaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWB)
|
||||
#define GICR_PBASER_WaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWT)
|
||||
#define GICR_PBASER_WaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWB)
|
||||
#define GICR_PBASER_RaWaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWT)
|
||||
#define GICR_PBASER_RaWaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWB)
|
||||
|
||||
#define GIC_EPPI_BASE_INTID 1056
|
||||
#define GIC_ESPI_BASE_INTID 4096
|
||||
|
||||
#define GIC_IRQ_TYPE_LPI 0xa110c8ed
|
||||
#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
|
||||
|
||||
#define read_gicreg(reg, out) rt_hw_sysreg_read(reg, out)
|
||||
#define write_gicreg(reg, in) rt_hw_sysreg_write(reg, in)
|
||||
|
||||
#define ICC_CTLR_EOImode 0x2
|
||||
#define ICC_PMR_MASK 0xff
|
||||
#define ICC_PMR_DEFAULT 0xf0
|
||||
#define ICC_IGRPEN1_EN 0x1
|
||||
|
||||
#define ICC_SGIR_AFF3_SHIFT 48
|
||||
#define ICC_SGIR_AFF2_SHIFT 32
|
||||
#define ICC_SGIR_AFF1_SHIFT 16
|
||||
#define ICC_SGIR_TARGET_MASK 0xffff
|
||||
#define ICC_SGIR_IRQN_SHIFT 24
|
||||
#define ICC_SGIR_ROUTING_BIT (1ULL << 40)
|
||||
|
||||
#define ICC_SGI1R_TARGET_LIST_SHIFT 0
|
||||
#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
|
||||
#define ICC_SGI1R_TARGET_LIST_MAX 16
|
||||
#define ICC_SGI1R_AFFINITY_1_SHIFT 16
|
||||
#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
|
||||
#define ICC_SGI1R_SGI_ID_SHIFT 24
|
||||
#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
|
||||
#define ICC_SGI1R_AFFINITY_2_SHIFT 32
|
||||
#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
|
||||
#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
|
||||
#define ICC_SGI1R_RS_SHIFT 44
|
||||
#define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
|
||||
#define ICC_SGI1R_AFFINITY_3_SHIFT 48
|
||||
#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
|
||||
|
||||
#define ICC_CTLR_EL1_CBPR_SHIFT 0
|
||||
#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
|
||||
#define ICC_CTLR_EL1_EOImode_SHIFT (1)
|
||||
#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
|
||||
#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
|
||||
#define ICC_CTLR_EL1_PRI_BITS_SHIFT (8)
|
||||
#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
|
||||
#define ICC_CTLR_EL1_RSS (0x1 << 18)
|
||||
#define ICC_CTLR_EL1_ExtRange (0x1 << 19)
|
||||
|
||||
struct gicv3
|
||||
{
|
||||
struct rt_pic parent;
|
||||
|
||||
int version;
|
||||
int irq_nr;
|
||||
rt_uint32_t gicd_typer;
|
||||
rt_size_t line_nr;
|
||||
rt_size_t espi_nr;
|
||||
rt_size_t lpi_nr;
|
||||
rt_ubase_t flags;
|
||||
|
||||
void *dist_base;
|
||||
rt_size_t dist_size;
|
||||
|
||||
void *redist_percpu_base[RT_CPUS_NR];
|
||||
rt_uint64_t redist_percpu_flags[RT_CPUS_NR];
|
||||
rt_size_t percpu_ppi_nr[RT_CPUS_NR];
|
||||
|
||||
struct
|
||||
{
|
||||
void *base;
|
||||
void *base_phy;
|
||||
rt_size_t size;
|
||||
} *redist_regions;
|
||||
rt_uint64_t redist_flags;
|
||||
rt_size_t redist_stride;
|
||||
rt_size_t redist_regions_nr;
|
||||
|
||||
rt_bool_t skip_init;
|
||||
};
|
||||
|
||||
#endif /* __PIC_GICV3_H__ */
|
||||
1319
RT_Thread/components/drivers/pic/pic.c
Normal file
1319
RT_Thread/components/drivers/pic/pic.c
Normal file
File diff suppressed because it is too large
Load Diff
79
RT_Thread/components/drivers/pic/pic_rthw.c
Normal file
79
RT_Thread/components/drivers/pic/pic_rthw.c
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-08-24 GuEe-GUI first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
/* initialize pic */
|
||||
rt_pic_irq_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
rt_pic_irq_mask(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
rt_pic_irq_unmask(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_pic_attach_irq(vector, handler, param, name, RT_IRQ_F_NONE);
|
||||
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
void rt_hw_interrupt_uninstall(int vector, rt_isr_handler_t handler, void *param)
|
||||
{
|
||||
rt_pic_detach_irq(vector, param);
|
||||
}
|
||||
|
||||
#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
|
||||
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
|
||||
{
|
||||
RT_BITMAP_DECLARE(cpu_masks, RT_CPUS_NR) = { cpu_mask };
|
||||
|
||||
rt_pic_irq_send_ipi(ipi_vector, cpu_masks);
|
||||
}
|
||||
|
||||
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
|
||||
{
|
||||
/* note: ipi_vector maybe different with irq_vector */
|
||||
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user