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冯佳
2025-06-19 21:56:46 +08:00
parent fe98e5f010
commit a4841450cf
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23
RT_Thread/libcpu/arm/sep4020/SConscript Normal file
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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += Glob('*_rvds.S')
if rtconfig.PLATFORM in ['gcc']:
src += Glob('*_init.S')
src += Glob('*_gcc.S')
if rtconfig.PLATFORM in ['iccarm']:
src += Glob('*_iar.S')
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

108
RT_Thread/libcpu/arm/sep4020/clk.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-20 zchong first version
*/
#include <rtthread.h>
#include "sep4020.h"
#define CLK_IN 4000000 /* Fin = 4.00MHz */
#define SYSCLK 72000000 /* system clock we want */
#define CLK_ESRAM 0
#define CLK_LCDC 1
#define CLK_PWM 2
#define CLK_DMAC 3
#define CLK_EMI 4
#define CLK_MMCSD 5
#define CLK_SSI 7
#define CLK_UART0 8
#define CLK_UART1 9
#define CLK_UART2 10
#define CLK_UART3 11
#define CLK_USB 12
#define CLK_MAC 13
#define CLK_SMC 14
#define CLK_I2C 15
#define CLK_GPT 16
static void rt_hw_set_system_clock(void)
{
rt_uint8_t pv;
/* pv value*/
pv = SYSCLK/2/CLK_IN;
/* go to normal mode*/
*(RP)PMU_PMDR = 0x01;
/* set the clock */
*(RP)PMU_PMCR = 0x4000 | pv;
/* trige configurate*/
*(RP)PMU_PMCR = 0xc000 | pv;
}
static void rt_hw_set_usb_clock(void)
{
/* set the clock */
*(RP)PMU_PUCR = 0x000c;
/* trige configurate*/
*(RP)PMU_PMCR = 0x800c;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
/* set system clock */
rt_hw_set_system_clock();
/* set usb clock */
rt_hw_set_usb_clock();
}
/**
* @brief Get system clock
*/
rt_uint32_t rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t pv, pd, npd;
/* get PMCR value */
val =*(RP) PMU_PMCR;
/* get NPD */
npd = (val >> 14) & 0x01;
/* get PD */
pd = (val >> 10) & 0x0f;
/* get PV */
pv = val & 0x7f;
/* caculate the system clock */
if(npd)
val = 2 * CLK_IN * pv;
else
val = CLK_IN * pv / (pd + 1);
return(val);
}
/**
* @brief Enable module clock
*/
void rt_hw_enable_module_clock(rt_uint8_t module)
{
}
/**
* @brief Disable module clock
*/
void rt_hw_disable_module_clock(rt_uint8_t module)
{
}

103
RT_Thread/libcpu/arm/sep4020/context_rvds.S Normal file
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;/*
; * Copyright (c) 2006-2022, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
BX lr
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
BX lr
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
STMFD sp!, {r0-r12, lr} ; push lr & register file
MRS r4, cpsr
STMFD sp!, {r4} ; push cpsr
MRS r4, spsr
STMFD sp!, {r4} ; push spsr
STR sp, [r0] ; store sp in preempted tasks TCB
LDR sp, [r1] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
LDR sp, [r0] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
BX lr
ENDP
END

172
RT_Thread/libcpu/arm/sep4020/cpu.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rtthread.h>
#include <sep4020.h>
extern rt_base_t rt_hw_interrupt_disable(void);
//TODO
#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* enable watchdog */
*(RP)(RTC_CTR) = 0x02;
/*Enable watchdog reset*/
*(RP)(RTC_INT_EN) = 0x20;
/* Initialize watchdog timer count register */
*(RP)(RTC_WD_CNT) = 0x0001;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/*@}*/

131
RT_Thread/libcpu/arm/sep4020/interrupt.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include <sep4020.h>
#define MAX_HANDLERS 32
extern rt_atomic_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/**
* @addtogroup S3C24X0
*/
/*@{*/
static void rt_hw_interrupt_handle(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
register rt_uint32_t idx;
/*Make sure all intc registers in proper state*/
/*mask all the irq*/
*(RP)(INTC_IMR) = 0xFFFFFFFF;
/*enable all the irq*/
*(RP)(INTC_IER) = 0XFFFFFFFF;
/*Dont use any forced irq*/
*(RP)(INTC_IFR) = 0x0;
/*Disable all the fiq*/
*(RP)(INTC_FIER) = 0x0;
/*Mask all the fiq*/
*(RP)(INTC_FIMR) = 0x0F;
/*Dont use forced fiq*/
*(RP)(INTC_FIFR) = 0x0;
/*Intrrupt priority register*/
*(RP)(INTC_IPLR) = 0x0;
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
for(idx=0; idx < MAX_HANDLERS; idx++)
{
isr_table[idx].handler = rt_hw_interrupt_handle;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
*(RP)(INTC_IMR) |= 1 << vector;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if(vector == 16)
{
rt_kprintf("Interrupt vec %d is not used!\n", vector);
}
else
*(RP)(INTC_IMR) &= ~(1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if(vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
/*@}*/

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RT_Thread/libcpu/arm/sep4020/sep4020.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __SEP4020_H
#define __SEP4020_H
#include <rtthread.h>
/*Core definations*/
#define SVCMODE
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x13
#define Mode_ABT 0x17
#define Mode_UND 0x1B
#define Mode_SYS 0x1F
/*
* 各模块寄存器基值
*/
#define ESRAM_BASE 0x04000000
#define INTC_BASE 0x10000000
#define PMU_BASE 0x10001000
#define RTC_BASE 0x10002000
#define WD_BASE 0x10002000
#define TIMER_BASE 0x10003000
#define PWM_BASE 0x10004000
#define UART0_BASE 0X10005000
#define UART1_BASE 0X10006000
#define UART2_BASE 0X10007000
#define UART3_BASE 0X10008000
#define SSI_BASE 0X10009000
#define I2S_BASE 0x1000A000
#define MMC_BASE 0x1000B000
#define SD_BASE 0x1000B000
#define SMC0_BASE 0x1000C000
#define SMC1_BASE 0x1000D000
#define USBD_BASE 0x1000E000
#define GPIO_BASE 0x1000F000
#define EMI_BASE 0x11000000
#define DMAC_BASE 0x11001000
#define LCDC_BASE 0x11002000
#define MAC_BASE 0x11003000
#define AMBA_BASE 0x11005000
/*
* INTC模块
* 基址: 0x10000000
*/
#define INTC_IER (INTC_BASE+0X000) /* IRQ中断允许寄存器 */
#define INTC_IMR (INTC_BASE+0X008) /* IRQ中断屏蔽寄存器 */
#define INTC_IFR (INTC_BASE+0X010) /* IRQ软件强制中断寄存器 */
#define INTC_IRSR (INTC_BASE+0X018) /* IRQ未处理中断状态寄存器 */
#define INTC_ISR (INTC_BASE+0X020) /* IRQ中断状态寄存器 */
#define INTC_IMSR (INTC_BASE+0X028) /* IRQ屏蔽中断状态寄存器 */
#define INTC_IFSR (INTC_BASE+0X030) /* IRQ中断最终状态寄存器 */
#define INTC_FIER (INTC_BASE+0X0C0) /* FIQ中断允许寄存器 */
#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQ中断屏蔽寄存器 */
#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQ软件强制中断寄存器 */
#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQ未处理中断状态寄存器 */
#define INTC_FISR (INTC_BASE+0X0D0) /* FIQ中断状态寄存器 */
#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQ中断最终状态寄存器 */
#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQ中断优先级寄存器 */
#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQ内部中断优先级控制寄存器1 */
#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQ内部中断优先级控制寄存器2 */
#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQ外部中断优先级控制寄存器1 */
#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQ外部中断优先级控制寄存器2 */
/*
* PMU模块
* 基址: 0x10001000
*/
#define PMU_PLTR (PMU_BASE+0X000) /* PLL的稳定过渡时间 */
#define PMU_PMCR (PMU_BASE+0X004) /* 系统主时钟PLL的控制寄存器 */
#define PMU_PUCR (PMU_BASE+0X008) /* USB时钟PLL的控制寄存器 */
#define PMU_PCSR (PMU_BASE+0X00C) /* 内部模块时钟源供给的控制寄存器 */
#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW状态下时钟的分频因子 */
#define PMU_PMDR (PMU_BASE+0X014) /* 芯片工作模式寄存器 */
#define PMU_RCTR (PMU_BASE+0X018) /* Reset控制寄存器 */
#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUp清除寄存器 */
/*
* RTC模块
* 基址: 0x10002000
*/
#define RTC_STA_YMD (RTC_BASE+0X000) /* 年, 月, 日计数寄存器 */
#define RTC_STA_HMS (RTC_BASE+0X004) /* 小时, 分钟, 秒寄存器 */
#define RTC_ALARM_ALL (RTC_BASE+0X008) /* 定时月, 日, 时, 分寄存器 */
#define RTC_CTR (RTC_BASE+0X00C) /* 控制寄存器 */
#define RTC_INT_EN (RTC_BASE+0X010) /* 中断使能寄存器 */
#define RTC_INT_STS (RTC_BASE+0X014) /* 中断状态寄存器 */
#define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */
#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */
#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */
#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* 配置时间确认寄存器 (在配置时间之前先写0xaaaaaaaa) */
#define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */
/*
* TIMER模块
* 基址: 0x10003000
*/
#define TIMER_T1LCR (TIMER_BASE+0X000) /* 通道1加载计数寄存器 */
#define TIMER_T1CCR (TIMER_BASE+0X004) /* 通道1当前计数值寄存器 */
#define TIMER_T1CR (TIMER_BASE+0X008) /* 通道1控制寄存器 */
#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* 通道1中断状态清除寄存器 */
#define TIMER_T1IMSR (TIMER_BASE+0X010) /* 通道1中断屏蔽状态寄存器 */
#define TIMER_T2LCR (TIMER_BASE+0X020) /* 通道2加载计数寄存器 */
#define TIMER_T2CCR (TIMER_BASE+0X024) /* 通道2当前计数值寄存器 */
#define TIMER_T2CR (TIMER_BASE+0X028) /* 通道2控制寄存器 */
#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* 通道2中断状态清除寄存器 */
#define TIMER_T2IMSR (TIMER_BASE+0X030) /* 通道2中断屏蔽状态寄存器 */
#define TIMER_T3LCR (TIMER_BASE+0X040) /* 通道3加载计数寄存器 */
#define TIMER_T3CCR (TIMER_BASE+0X044) /* 通道3当前计数值寄存器 */
#define TIMER_T3CR (TIMER_BASE+0X048) /* 通道3控制寄存器 */
#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* 通道3中断状态清除寄存器 */
#define TIMER_T3IMSR (TIMER_BASE+0X050) /* 通道3中断屏蔽状态寄存器 */
#define TIMER_T3CAPR (TIMER_BASE+0X054) /* 通道3捕获寄存器 */
#define TIMER_T4LCR (TIMER_BASE+0X060) /* 通道4加载计数寄存器 */
#define TIMER_T4CCR (TIMER_BASE+0X064) /* 通道4当前计数值寄存器 */
#define TIMER_T4CR (TIMER_BASE+0X068) /* 通道4控制寄存器 */
#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* 通道4中断状态清除寄存器 */
#define TIMER_T4IMSR (TIMER_BASE+0X070) /* 通道4中断屏蔽状态寄存器 */
#define TIMER_T4CAPR (TIMER_BASE+0X074) /* 通道4捕获寄存器 */
#define TIMER_T5LCR (TIMER_BASE+0X080) /* 通道5加载计数寄存器 */
#define TIMER_T5CCR (TIMER_BASE+0X084) /* 通道5当前计数值寄存器 */
#define TIMER_T5CR (TIMER_BASE+0X088) /* 通道5控制寄存器 */
#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* 通道5中断状态清除寄存器 */
#define TIMER_T5IMSR (TIMER_BASE+0X090) /* 通道5中断屏蔽状态寄存器 */
#define TIMER_T5CAPR (TIMER_BASE+0X094) /* 通道5捕获寄存器 */
#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* 通道6加载计数寄存器 */
#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* 通道6当前计数值寄存器 */
#define TIMER_T6CR (TIMER_BASE+0X0A8) /* 通道6控制寄存器 */
#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* 通道6中断状态清除寄存器 */
#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* 通道6中断屏蔽状态寄存器 */
#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* 通道6捕获寄存器 */
#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* 通道7加载计数寄存器 */
#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* 通道7当前计数值寄存器 */
#define TIMER_T7CR (TIMER_BASE+0X0C8) /* 通道7控制寄存器 */
#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* 通道7中断状态清除寄存器 */
#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* 通道7中断屏蔽状态寄存器 */
#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* 通道8加载计数寄存器 */
#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* 通道8当前计数值寄存器 */
#define TIMER_T8CR (TIMER_BASE+0X0E8) /* 通道8控制寄存器 */
#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* 通道8中断状态清除寄存器 */
#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* 通道8中断屏蔽状态寄存器 */
#define TIMER_T9LCR (TIMER_BASE+0X100) /* 通道9加载计数寄存器 */
#define TIMER_T9CCR (TIMER_BASE+0X104) /* 通道9当前计数值寄存器 */
#define TIMER_T9CR (TIMER_BASE+0X108) /* 通道9控制寄存器 */
#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* 通道9中断状态清除寄存器 */
#define TIMER_T9IMSR (TIMER_BASE+0X110) /* 通道9中断屏蔽状态寄存器 */
#define TIMER_T10LCR (TIMER_BASE+0X120) /* 通道10加载计数寄存器 */
#define TIMER_T10CCR (TIMER_BASE+0X124) /* 通道10当前计数值寄存器 */
#define TIMER_T10CR (TIMER_BASE+0X128) /* 通道10控制寄存器 */
#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* 通道10中断状态清除寄存器 */
#define TIMER_T10IMSR (TIMER_BASE+0X130) /* 通道10中断屏蔽状态寄存器 */
#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMER中断屏蔽状态寄存器 */
#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMER中断状态清除寄存器 */
#define TIMER_TISR (TIMER_BASE+0X148) /* TIMER中断状态寄存器 */
/*
* PWM模块
* 基址: 0x10004000
*/
#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0控制寄存器 */
#define PWM0_DIV (PWM_BASE+0X004) /* PWM0分频寄存器 */
#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0周期寄存器 */
#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0数据寄存器 */
#define PWM0_CNT (PWM_BASE+0X010) /* PWM0计数寄存器 */
#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0状态寄存器 */
#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1控制寄存器 */
#define PWM1_DIV (PWM_BASE+0X024) /* PWM1分频寄存器 */
#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1周期寄存器 */
#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1数据寄存器 */
#define PWM1_CNT (PWM_BASE+0X030) /* PWM1计数寄存器 */
#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1状态寄存器 */
#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2控制寄存器 */
#define PWM2_DIV (PWM_BASE+0X044) /* PWM2分频寄存器 */
#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2周期寄存器 */
#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2数据寄存器 */
#define PWM2_CNT (PWM_BASE+0X050) /* PWM2计数寄存器 */
#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2状态寄存器 */
#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3控制寄存器 */
#define PWM3_DIV (PWM_BASE+0X064) /* PWM3分频寄存器 */
#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3周期寄存器 */
#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3数据寄存器 */
#define PWM3_CNT (PWM_BASE+0X070) /* PWM3计数寄存器 */
#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3状态寄存器 */
#define PWM_INTMASK (PWM_BASE+0X080) /* PWM中断屏蔽寄存器 */
#define PWM_INT (PWM_BASE+0X084) /* PWM中断寄存器 */
#define PWM_ENABLE (PWM_BASE+0X088) /* PWM使能寄存器 */
/*
* UART0模块
* 基址: 0x10005000
*/
#define UART0_DLBL (UART0_BASE+0X000) /* 波特率设置低八位寄存器 */
#define UART0_RXFIFO (UART0_BASE+0X000) /* 接收FIFO */
#define UART0_TXFIFO (UART0_BASE+0X000) /* 发送FIFO */
#define UART0_DLBH (UART0_BASE+0X004) /* 波特率设置高八位寄存器 */
#define UART0_IER (UART0_BASE+0X004) /* 中断使能寄存器 */
#define UART0_IIR (UART0_BASE+0X008) /* 中断识别寄存器 */
#define UART0_FCR (UART0_BASE+0X008) /* FIFO控制寄存器 */
#define UART0_LCR (UART0_BASE+0X00C) /* 行控制寄存器 */
#define UART0_MCR (UART0_BASE+0X010) /* Modem控制寄存器 */
#define UART0_LSR (UART0_BASE+0X014) /* 行状态寄存器 */
#define UART0_MSR (UART0_BASE+0X018) /* Modem状态寄存器 */
/*
* UART1模块
* 基址: 0x10006000
*/
#define UART1_DLBL (UART1_BASE+0X000) /* 波特率设置低八位寄存器 */
#define UART1_RXFIFO (UART1_BASE+0X000) /* 接收FIFO */
#define UART1_TXFIFO (UART1_BASE+0X000) /* 发送FIFO */
#define UART1_DLBH (UART1_BASE+0X004) /* 波特率设置高八位寄存器 */
#define UART1_IER (UART1_BASE+0X004) /* 中断使能寄存器 */
#define UART1_IIR (UART1_BASE+0X008) /* 中断识别寄存器 */
#define UART1_FCR (UART1_BASE+0X008) /* FIFO控制寄存器 */
#define UART1_LCR (UART1_BASE+0X00C) /* 行控制寄存器 */
#define UART1_MCR (UART1_BASE+0X010) /* Modem控制寄存器 */
#define UART1_LSR (UART1_BASE+0X014) /* 行状态寄存器 */
#define UART1_MSR (UART1_BASE+0X018) /* Modem状态寄存器 */
/*
* UART2模块
* 基址: 0x10007000
*/
#define UART2_DLBL (UART2_BASE+0X000) /* 波特率设置低八位寄存器 */
#define UART2_RXFIFO (UART2_BASE+0X000) /* 接收FIFO */
#define UART2_TXFIFO (UART2_BASE+0X000) /* 发送FIFO */
#define UART2_DLBH (UART2_BASE+0X004) /* 波特率设置高八位寄存器 */
#define UART2_IER (UART2_BASE+0X004) /* 中断使能寄存器 */
#define UART2_IIR (UART2_BASE+0X008) /* 中断识别寄存器 */
#define UART2_FCR (UART2_BASE+0X008) /* FIFO控制寄存器 */
#define UART2_LCR (UART2_BASE+0X00C) /* 行控制寄存器 */
#define UART2_MCR (UART2_BASE+0X010) /* Modem控制寄存器 */
#define UART2_LSR (UART2_BASE+0X014) /* 行状态寄存器 */
#define UART2_MSR (UART2_BASE+0X018) /* Modem状态寄存器 */
/*
* UART3模块
* 基址: 0x10008000
*/
#define UART3_DLBL (UART3_BASE+0X000) /* 波特率设置低八位寄存器 */
#define UART3_RXFIFO (UART3_BASE+0X000) /* 接收FIFO */
#define UART3_TXFIFO (UART3_BASE+0X000) /* 发送FIFO */
#define UART3_DLBH (UART3_BASE+0X004) /* 波特率设置高八位寄存器 */
#define UART3_IER (UART3_BASE+0X004) /* 中断使能寄存器 */
#define UART3_IIR (UART3_BASE+0X008) /* 中断识别寄存器 */
#define UART3_FCR (UART3_BASE+0X008) /* FIFO控制寄存器 */
#define UART3_LCR (UART3_BASE+0X00C) /* 行控制寄存器 */
#define UART3_MCR (UART3_BASE+0X010) /* Modem控制寄存器 */
#define UART3_LSR (UART3_BASE+0X014) /* 行状态寄存器 */
#define UART3_MSR (UART3_BASE+0X018) /* Modem状态寄存器 */
/*
* SSI模块
* 基址: 0x10009000
*/
#define SSI_CONTROL0 (SSI_BASE+0X000) /* 控制寄存器0 */
#define SSI_CONTROL1 (SSI_BASE+0X004) /* 控制寄存器1 */
#define SSI_SSIENR (SSI_BASE+0X008) /* SSI使能寄存器 */
#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire控制寄存器 */
#define SSI_SER (SSI_BASE+0X010) /* 从设备使能寄存器 */
#define SSI_BAUDR (SSI_BASE+0X014) /* 波特率设置寄存器 */
#define SSI_TXFTLR (SSI_BASE+0X018) /* 发送FIFO阈值寄存器 */
#define SSI_RXFTLR (SSI_BASE+0X01C) /* 接收FIFO阈值寄存器 */
#define SSI_TXFLR (SSI_BASE+0X020) /* 发送FIFO状态寄存器 */
#define SSI_RXFLR (SSI_BASE+0X024) /* 接收FIFO状态寄存器 */
#define SSI_SR (SSI_BASE+0X028) /* 状态寄存器 */
#define SSI_IMR (SSI_BASE+0X02C) /* 中断屏蔽寄存器 */
#define SSI_ISR (SSI_BASE+0X030) /* 中断最终状态寄存器 */
#define SSI_RISR (SSI_BASE+0X034) /* 中断原始状态寄存器 */
#define SSI_TXOICR (SSI_BASE+0X038) /* 发送FIFO上溢中断清除寄存器 */
#define SSI_RXOICR (SSI_BASE+0X03C) /* 接收FIFO上溢中断清除寄存器 */
#define SSI_RXUICR (SSI_BASE+0X040) /* 接收FIFO下溢中断清除寄存器 */
#define SSI_ICR (SSI_BASE+0X02C) /* 中断清除寄存器 */
#define SSI_DMACR (SSI_BASE+0X04C) /* DMA控制寄存器 */
#define SSI_DMATDLR (SSI_BASE+0X050) /* DMA发送状态寄存器 */
#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA接收状态寄存器 */
#define SSI_DR (SSI_BASE+0X060) /* 数据寄存器 */
/*
* I2S模块
* 基址: 0x1000A000
*/
#define I2S_CTRL (I2S_BASE+0X000) /* I2S控制寄存器 */
#define I2S_DATA (I2S_BASE+0X004) /* I2S数据寄存器 */
#define I2S_INT (I2S_BASE+0X008) /* I2S中断寄存器 */
#define I2S_STATUS (I2S_BASE+0X00C) /* I2S状态寄存器 */
/*
* SD模块
* 基址: 0x1000B000
*/
#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */
#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */
#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */
#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */
#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO数据块长度寄存器 */
#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */
#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */
#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */
#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */
#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */
#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */
#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */
#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状态寄存器 */
#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状态屏蔽寄存器 */
#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO接收FIFO */
#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO发送FIFO */
/*
* SMC0模块
* 基址: 0x1000C000
*/
#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0控制寄存器 */
#define SMC0_INT (SMC0_BASE+0X004) /* SMC0中断寄存器 */
#define SMC0_FD (SMC0_BASE+0X008) /* SMC0基本单元时间寄存器 */
#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0字符传输时间寄存器 */
#define SMC0_BT (SMC0_BASE+0X010) /* SMC0块传输时间寄存器 */
/*
* SMC1模块
* 基址: 0x1000D000
*/
#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1控制寄存器 */
#define SMC1_INT (SMC1_BASE+0X004) /* SMC1中断寄存器 */
#define SMC1_FD (SMC1_BASE+0X008) /* SMC1基本单元时间寄存器 */
#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1字符传输时间寄存器 */
#define SMC1_BT (SMC1_BASE+0X010) /* SMC1块传输时间寄存器 */
/*
* USBD模块
* 基址: 0x1000E000
*/
#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USB协议中断寄存器 */
#define USBD_INTRMASK (USBD_BASE+0X004) /* USB中断屏蔽寄存器 */
#define USBD_INTRCTRL (USBD_BASE+0X008) /* USB中断类型控制寄存器 */
#define USBD_EPINFO (USBD_BASE+0X00C) /* USB活动端点状态寄存器 */
#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION记录 */
#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* 当前配置属性寄存器 */
#define USBD_DEVSPEED (USBD_BASE+0X018) /* 当前设备工作速度寄存器 */
#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* 记录当前SOF包内的帧号 */
#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* 记录下次要求的传输次数 */
#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* 记录下次要求的传输次数 */
#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* 接口号快速更新寄存器 */
#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* 记录接口的值 */
#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* 记录接口的值 */
#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* 记录接口的值 */
#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* 记录接口的值 */
#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* 记录接口的值 */
#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* 记录接口的值 */
#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* 记录接口的值 */
#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* 记录接口的值 */
#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* 记录接口的值 */
#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* 记录接口的值 */
#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* 记录接口的值 */
#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* 记录接口的值 */
#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* 记录接口的值 */
#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* 记录接口的值 */
#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* 记录接口的值 */
#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* 记录接口的值 */
#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* 记录接口的值 */
#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* 记录接口的值 */
#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* 记录接口的值 */
#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* 记录接口的值 */
#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* 记录接口的值 */
#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* 记录接口的值 */
#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* 记录接口的值 */
#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* 记录接口的值 */
#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* 记录接口的值 */
#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* 记录接口的值 */
#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* 记录接口的值 */
#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* 记录接口的值 */
#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* 记录接口的值 */
#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* 记录接口的值 */
#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* 记录接口的值 */
#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* 记录接口的值 */
#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* 记录成功接收的包数 */
#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* 记录丢失的包数 */
#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* 记录CRC错误的包数 */
#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* 记录位填充错误的包数 */
#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* 记录PID错误的包数 */
#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* 记录有SYNC和EOP的包数 */
#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* 记录发送包的数量 */
#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* 记录统计寄存器溢出情况 */
#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* 记录每次IN传输事务包长度 */
#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* 记录OUT传输事务包长度 */
#define USBD_RESUME (USBD_BASE+0X0D4) /* USB唤醒寄存器 */
#define USBD_READFLAG (USBD_BASE+0X0D8) /* 读异步状态寄存器标志 */
#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* 传输状态寄存器 */
#define USBD_APPLOCK (USBD_BASE+0X0E0) /* 锁信号寄存器 */
#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* 端点0端点号和方向 */
#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* 端点0类型寄存器 */
#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* 端点0最大包尺寸寄存器 */
#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* 端点0接口号寄存器 */
#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* 端点0状态寄存器 */
#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* 端点0 SETUP事务请求类 */
#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* 端点0 SETUP事务请求内容 */
#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* 端点0 SETUP事务请求值 */
#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* 端点0 SETUP事务请求索引 */
#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* 端点0 SETUP事务请求长度 */
#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* 端点0同步包帧号 */
#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* 端点1输出端点号和方向 */
#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* 端点1输出类型寄存器 */
#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* 端点1输出最大包尺寸寄存器 */
#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* 端点1输出接口号寄存器 */
#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* 端点1输出状态寄存器 */
#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* 端点1输出SETUP事务请求类型 */
#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* 端点1输出SETUP事务请求内容 */
#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* 端点1输出SETUP事务请求值 */
#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* 端点1输出SETUP事务请求索引 */
#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* 端点1输出SETUP事务请求域长度 */
#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* 端点1输出同步包帧号 */
#define USBD_EP1INADDR (USBD_BASE+0X158) /* 端点1输入端点号和方向 */
#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* 端点1输入类型寄存器 */
#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* 端点1输入最大包尺寸寄存器 */
#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* 端点1输入接口号寄存器 */
#define USBD_EP1INSTAT (USBD_BASE+0X168) /* 端点1输入状态寄存器 */
#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* 端点1输入SETUP事务请求类型 */
#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* 端点1输入SETUP事务请求内容 */
#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* 端点1输入SETUP事务请求值 */
#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* 端点1输入SETUP事务请求索引 */
#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* 端点1输入SETUP事务请求域长度 */
#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* 端点1输入同步包帧号 */
#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* 端点2输出端点号和方向 */
#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* 端点2输出类型寄存器 */
#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* 端点2输出最大包尺寸寄存器 */
#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* 端点2输出接口号寄存器 */
#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* 端点2输出状态寄存器 */
#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* 端点2输出SETUP事务请求类型 */
#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* 端点2输出SETUP事务请求内容 */
#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* 端点2输出SETUP事务请求值 */
#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* 端点2输出SETUP事务请求索引 */
#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* 端点2输出SETUP事务请求域长度 */
#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* 端点2输出同步包帧号 */
#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* 端点2输入端点号和方向 */
#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* 端点2输入类型寄存器 */
#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* 端点2输入最大包尺寸寄存器 */
#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* 端点2输入接口号寄存器 */
#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* 端点2输入状态寄存器 */
#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* 端点2输入SETUP事务请求类型 */
#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* 端点2输入SETUP事务请求内容 */
#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* 端点2输入SETUP事务请求值 */
#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* 端点2输入SETUP事务请求索引 */
#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* 端点2输入SETUP事务请求域长度 */
#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* 端点2输入同步包帧号 */
#define USBD_RXFIFO (USBD_BASE+0X200) /* 接受FIFO */
#define USBD_TXFIFO (USBD_BASE+0X300) /* 发送FIFO */
/*
* GPIO模块
* 基址: 0x1000F000
*/
#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* 去毛刺采用时钟分频比配置寄存器 */
#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A组端口输入输出方向配置寄存器 */
#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A组端口通用用途选择配置寄存器 */
#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A组端口通用用途输入时类型配置寄存器 */
#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A组端口中断触发类型配置寄存器 */
#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A组端口通用用途中断清除配置寄存器 */
#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A组端口通用用途数据配置寄存器 */
#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B组端口输入输出方向配置寄存器 */
#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B组端口通用用途选择配置寄存器 */
#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B组端口通用用途数据配置寄存器 */
#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C组端口输入输出方向配置寄存器 */
#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C组端口通用用途选择配置寄存器 */
#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C组端口通用用途数据配置寄存器 */
#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D组端口输入输出方向配置寄存器 */
#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D组端口通用用途选择配置寄存器 */
#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D组端口专用用途2选择配置寄存器 */
#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D组端口通用用途数据配置寄存器 */
#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E组端口输入输出方向配置寄存器 */
#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E组端口通用用途选择配置寄存器 */
#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E组端口通用用途数据配置寄存器 */
#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F组端口输入输出方向配置寄存器 */
#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F组端口通用用途选择配置寄存器 */
#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F组端口通用用途输入时类型配置寄存器 */
#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F组端口中断触发类型配置寄存器 */
#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F组端口通用用途中断清除配置寄存器 */
#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F组端口通用用途数据配置寄存器 */
#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G组端口输入输出方向配置寄存器 */
#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G组端口通用用途选择配置寄存器 */
#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G组端口通用用途数据配置寄存器 */
#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H组端口输入输出方向配置寄存器 */
#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H组端口通用用途选择配置寄存器 */
#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H组端口通用用途数据配置寄存器 */
#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I组端口输入输出方向配置寄存器 */
#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I组端口通用用途选择配置寄存器 */
#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I组端口通用用途数据配置寄存器 */
/*
* EMI模块
* 基址: 0x11000000
*/
#define EMI_CSACONF (EMI_BASE+0X000) /* CSA参数配置寄存器 */
#define EMI_CSBCONF (EMI_BASE+0X004) /* CSB参数配置寄存器 */
#define EMI_CSCCONF (EMI_BASE+0X008) /* CSC参数配置寄存器 */
#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD参数配置寄存器 */
#define EMI_CSECONF (EMI_BASE+0X010) /* CSE参数配置寄存器 */
#define EMI_CSFCONF (EMI_BASE+0X014) /* CSF参数配置寄存器 */
#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAM时序配置寄存器1 */
#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAM时序配置寄存器2, SDRAM初始化用到的配置信息 */
#define EMI_REMAPCONF (EMI_BASE+0X020) /* 片选空间及地址映射REMAP配置寄存器 */
#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASH的地址寄存器1 */
#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASH的控制字寄存器 */
#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASH的状态寄存器 */
#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* 读操作出错的地址寄存器1 */
#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* 读操作出错的地址寄存器2 */
#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASH的配置器存器1 */
#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASH中断寄存器 */
#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECC校验完成寄存器 */
#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH空闲寄存器 */
#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASH的配置器存器2 */
#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASH的地址寄存器2 */
#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASH的数据寄存器 */
/*
* DMAC模块
* 基址: 0x11001000
*/
#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMC中断状态寄存器。 */
#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC传输完成中断状态寄存器 */
#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC传输完成中断状态清除寄存器 */
#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC传输错误中断状态寄存器 */
#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC传输错误中断状态清除寄存器 */
#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMAC通道使能状态寄存器 */
#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMAC道0源地址寄存器 */
#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMAC道0目的地址寄存器 */
#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMAC道0控制寄存器 */
#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMAC道0配置寄存器 */
#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMAC道0链表地址寄存器 */
#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMAC道1源地址寄存器 */
#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMAC道1目的地址寄存器 */
#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMAC道1控制寄存器 */
#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMAC道1配置寄存器 */
#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMAC道1链表地址寄存器 */
#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMAC道2源地址寄存器 */
#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMAC道2目的地址寄存器 */
#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMAC道2控制寄存器 */
#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMAC道2配置寄存器 */
#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMAC道2链表地址寄存器 */
#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMAC道3源地址寄存器 */
#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMAC道3目的地址寄存器 */
#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMAC道3控制寄存器 */
#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMAC道3配置寄存器 */
#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMAC道3链表地址寄存器 */
#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMAC道4源地址寄存器 */
#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMAC道4目的地址寄存器 */
#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMAC道4控制寄存器 */
#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMAC道4配置寄存器 */
#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMAC道4链表地址寄存器 */
#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMAC道5源地址寄存器 */
#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMAC道5目的地址寄存器 */
#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMAC道5控制寄存器 */
#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMAC道5配置寄存器 */
#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMAC道5链表地址寄存器 */
/*
* LCDC模块
* 基址: 0x11002000
*/
#define LCDC_SSA (LCDC_BASE+0X000) /* 屏幕起始地址寄存器 */
#define LCDC_SIZE (LCDC_BASE+0X004) /* 屏幕尺寸寄存器 */
#define LCDC_PCR (LCDC_BASE+0X008) /* 面板配置寄存器 */
#define LCDC_HCR (LCDC_BASE+0X00C) /* 水平配置寄存器 */
#define LCDC_VCR (LCDC_BASE+0X010) /* 垂直配置寄存器 */
#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM对比度控制寄存器 */
#define LCDC_LECR (LCDC_BASE+0X018) /* 使能控制寄存器 */
#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA控制寄存器 */
#define LCDC_LCDISREN (LCDC_BASE+0X020) /* 中断使能寄存器 */
#define LCDC_LCDISR (LCDC_BASE+0X024) /* 中断状态寄存器 */
#define LCDC_LGPMR (LCDC_BASE+0X040) /* 灰度调色映射寄存器组 (16个32bit寄存器) */
/*
* MAC模块
* 基址: 0x11003000
*/
#define MAC_CTRL (MAC_BASE+0X000) /* MAC控制寄存器 */
#define MAC_INTSRC (MAC_BASE+0X004) /* MAC中断源寄存器 */
#define MAC_INTMASK (MAC_BASE+0X008) /* MAC中断屏蔽寄存器 */
#define MAC_IPGT (MAC_BASE+0X00C) /* 连续帧间隔寄存器 */
#define MAC_IPGR1 (MAC_BASE+0X010) /* 等待窗口寄存器 */
#define MAC_IPGR2 (MAC_BASE+0X014) /* 等待窗口寄存器 */
#define MAC_PACKETLEN (MAC_BASE+0X018) /* 帧长度寄存器 */
#define MAC_COLLCONF (MAC_BASE+0X01C) /* 碰撞重发寄存器 */
#define MAC_TXBD_NUM (MAC_BASE+0X020) /* 发送描述符寄存器 */
#define MAC_FLOWCTRL (MAC_BASE+0X024) /* 流控寄存器 */
#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY控制寄存器 */
#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHY命令寄存器 */
#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHY地址寄存器 */
#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHY写数据寄存器 */
#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY读数据寄存器 */
#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY状态寄存器 */
#define MAC_ADDR0 (MAC_BASE+0X040) /* MAC地址寄存器 */
#define MAC_ADDR1 (MAC_BASE+0X044) /* MAC地址寄存器 */
#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */
#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */
#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */
#define MAC_TX_BD (MAC_BASE+0X400)
#define MAC_RX_BD (MAC_BASE+0X600)
/*
**************************************
* Error Codes:
* IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE,
* parameter error return (-33)/E_PAR,
* hardware error reture (-99)/E_HA
**************************************
*/
#define E_OK 0 /* Normal completion */
#define E_SYS (-5) /* System error */
#define E_NOMEM (-10) /* Insufficient memory */
#define E_NOSPT (-17) /* Feature not supported */
#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */
#define E_RSFN (-20) /* Reserved function code number */
#define E_RSATR (-24) /* Reserved attribute */
#define E_PAR (-33) /* Parameter error */
#define E_ID (-35) /* Invalid ID number */
#define E_NOEXS (-52) /* Object does not exist */
#define E_OBJ (-63) /* Invalid object state */
#define E_MACV (-65) /* Memory access disabled or memory access violation */
#define E_OACV (-66) /* Object access violation */
#define E_CTX (-69) /* Context error */
#define E_QOVR (-73) /* Queuing or nesting overflow */
#define E_DLT (-81) /* Object being waited for was deleted */
#define E_TMOUT (-85) /* Polling failure or timeout exceeded */
#define E_RLWAI (-86) /* WAIT state was forcibly released */
#define E_HA (-99) /* HARD WARE ERROR */
/*
**************************************
* PMU 模块时钟
**************************************
*/
#define CLK_SGPT (1 << 16)
#define CLK_SI2S (1 << 15)
#define CLK_SSMC (1 << 14)
#define CLK_SMAC (1 << 13)
#define CLK_SUSB (1 << 12)
#define CLK_SUART3 (1 << 11)
#define CLK_SUART2 (1 << 10)
#define CLK_SUART1 (1 << 9)
#define CLK_SUART0 (1 << 8)
#define CLK_SSSI (1 << 7)
#define CLK_SAC97 (1 << 6)
#define CLK_SMMCSD (1 << 5)
#define CLK_SEMI (1 << 4)
#define CLK_SDMAC (1 << 3)
#define CLK_SPWM (1 << 2)
#define CLK_SLCDC (1 << 1)
#define CLK_SESRAM (1)
/*Interrupt Sources*/
#define INTSRC_RTC 31
#define INTSRC_DMAC 30
#define INTSRC_EMI 29
#define INTSRC_MAC 28
#define INTSRC_TIMER1 27
#define INTSRC_TIMER2 26
#define INTSRC_TIMER3 25
#define INTSRC_UART0 24
#define INTSRC_UART1 23
#define INTSRC_UART2 22
#define INTSRC_UART3 21
#define INTSRC_PWM 20
#define INTSRC_LCDC 19
#define INTSRC_I2S 18
#define INTSRC_SSI 17
#define INTSRC_USB 15
#define INTSRC_SMC0 14
#define INTSRC_SMC1 13
#define INTSRC_SDIO 12
#define INTSRC_EXINT10 11
#define INTSRC_EXINT9 10
#define INTSRC_EXINT8 9
#define INTSRC_EXINT7 8
#define INTSRC_EXINT6 7
#define INTSRC_EXINT5 6
#define INTSRC_EXINT4 5
#define INTSRC_EXINT3 4
#define INTSRC_EXINT2 3
#define INTSRC_EXINT1 2
#define INTSRC_EXINT0 1
#define INTSRC_NULL 0
/*Sereral useful macros*/
#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //设置普通中断的优先级门限，只有优先级大于此值的中断才能通过
#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //置1后，软件强制该位对应的中断源发出中断信号
#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //置1后，允许中断源的IRQ 中断信号
#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //置0后，不允许中断源的IRQ 中断信号
#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号
#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //置0后，通过对应的IRQ 中断信号
#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //屏蔽对应的IRQ 中断信号
#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ 中断信号
#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //允许中断源的IRQ 中断信号
#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //不允许中断源的IRQ 中断信号
#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0)
/*
**************************************
* 所有程序中用到的Typedef
**************************************
*/
typedef char S8; /* signed 8-bit integer */
typedef short S16; /* signed 16-bit integer */
typedef long S32; /* signed 32-bit integer */
typedef unsigned char U8; /* unsigned 8-bit integer */
typedef unsigned short U16; /* unsigned 16-bit integer */
typedef unsigned long U32; /* unsigned 32-bit integer */
typedef volatile U32 * RP;
typedef volatile U16 * RP16;
typedef volatile U8 * RP8;
typedef void *VP; /* pointer to an unpredictable data type */
typedef void (*FP)(); /* program start address */
#ifndef _BOOL_TYPE_
#define _BOOL_TYPE_
typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */
#endif
typedef int ER; /* Error code. A signed integer. */
/**
* IO definitions
*
* define access restrictions to peripheral registers
*/
#define __I volatile const /*!< defines 'read only' permissions */
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
#define __iomem volatile
/*Macros for debug*/
#define EOUT(fmt,...) \
do \
{ \
rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \
rt_kprintf(fmt,##__VA_ARGS__); \
}while(0)
#define RT_USING_DEBUG
#ifdef RT_USING_DEBUG
#define DBOUT(fmt,...) \
do \
{ \
rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \
rt_kprintf(fmt,##__VA_ARGS__); \
}while(0)
#else
#define DBOUT(fmt,...) \
do{}while(0)
#endif
#ifdef RT_USING_DEBUG
#define ASSERT(arg) \
if((arg) == 0) \
{ \
while(1) \
{ \
rt_kprintf("have a assert failure\n"); \
} \
}
#else
#define ASSERT(arg) \
do \
{ \
}while(0)
#endif
#define write_reg(reg,value) \
do \
{ \
*(RP)(reg) = value; \
}while(0)
#define read_reg(reg) (*(RP)reg)
struct rt_hw_register
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
};
/*@}*/
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2009-04-20 yi.qiu modified according bernard's stm32 version
* 2010-10-6 wangmeng added sep4020 surpport
*/
#include <rtthread.h>
#include <rthw.h>
#include "serial.h"
/**
* @addtogroup SEP4020
*/
/*@{*/
/* RT-Thread Device Interface */
/**
* This function initializes serial
*/
static rt_err_t rt_serial_init (rt_device_t dev)
{
struct serial_device* uart = (struct serial_device*) dev->user_data;
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
rt_memset(uart->int_rx->rx_buffer, 0,
sizeof(uart->int_rx->rx_buffer));
uart->int_rx->read_index = uart->int_rx->save_index = 0;
}
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
rt_memset(uart->int_tx->tx_buffer, 0,
sizeof(uart->int_tx->tx_buffer));
uart->int_tx->write_index = uart->int_tx->save_index = 0;
}
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
return RT_EOK;
}
/* save a char to serial buffer */
static void rt_serial_savechar(struct serial_device* uart, char ch)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
uart->int_rx->save_index ++;
if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (uart->int_rx->save_index == uart->int_rx->read_index)
{
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_ssize_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct serial_device* uart;
ptr = buffer;
err_code = RT_EOK;
uart = (struct serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
rt_base_t level;
/* interrupt mode Rx */
while (size)
{
if (uart->int_rx->read_index != uart->int_rx->save_index)
{
*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
size --;
/* disable interrupt */
level = rt_hw_interrupt_disable();
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
else
{
/* set error code */
err_code = -RT_EEMPTY;
break;
}
}
}
else
{
/* polling mode */
while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
{
while (uart->uart_device->lsr & USTAT_RCV_READY)
{
*ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff;
ptr ++;
}
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_ssize_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct serial_device* uart;
err_code = RT_EOK;
ptr = (rt_uint8_t*)buffer;
uart = (struct serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* interrupt mode Tx */
while (uart->int_tx->save_index != uart->int_tx->write_index)
{
/* save on tx buffer */
uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-- size;
/* move to next position */
uart->int_tx->save_index ++;
/* wrap save index */
if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
uart->int_tx->save_index = 0;
}
/* set error code */
if (size > 0)
err_code = -RT_EFULL;
}
else
{
/* polling mode */
while (size)
{
/*
* to be polite with serial console add a line feed
* to the carriage return character
*/
if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
{
while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
uart->uart_device->dlbl_fifo.txfifo = '\r';
}
while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF);
++ptr; --size;
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
break;
}
return RT_EOK;
}
/*
* serial register
*/
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
{
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Char;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_serial_init;
device->open = rt_serial_open;
device->close = rt_serial_close;
device->read = rt_serial_read;
device->write = rt_serial_write;
device->control = rt_serial_control;
device->user_data = serial;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/* ISR for serial interrupt */
void rt_hw_serial_isr(rt_device_t device)
{
struct serial_device* uart = (struct serial_device*) device->user_data;
/* interrupt mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
/* save on rx buffer */
while (uart->uart_device->lsr & USTAT_RCV_READY)
{
rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff);
}
/* invoke callback */
if (device->rx_indicate != RT_NULL)
{
rt_size_t rx_length;
/* get rx length */
rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
uart->int_rx->save_index - uart->int_rx->read_index;
device->rx_indicate(device, rx_length);
}
}
/*@}*/

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2009-04-20 yi.qiu modified according bernard's stm32 version
* 2010-10-6 wangmeng added sep4020 surpport
*/
#ifndef __SERIAL_H__
#define __SERIAL_H__
#include <sep4020.h>
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
/*For sep4020's uart have several secondary function*/
/*we use union to decribe it*/
union dlbl_fifo
{
rt_uint32_t dlbl;
rt_uint32_t rxfifo;
rt_uint32_t txfifo;
};
union dlbh_ier
{
rt_uint32_t dlbh;
rt_uint32_t ier;
};
union iir_fcr
{
rt_uint32_t iir;
rt_uint32_t fcr;
};
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
union dlbl_fifo dlbl_fifo;
union dlbh_ier dlbh_ier;
union iir_fcr iir_fcr;
rt_uint32_t lcr;
rt_uint32_t mcr;
rt_uint32_t lsr;
rt_uint32_t msr;
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard the first version
*/
#include <rtthread.h>
#include <sep4020.h>
/**
* @addtogroup S3C24X0
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0xdeadbeef; /* r12 */
*(--stk) = 0xdeadbeef; /* r11 */
*(--stk) = 0xdeadbeef; /* r10 */
*(--stk) = 0xdeadbeef; /* r9 */
*(--stk) = 0xdeadbeef; /* r8 */
*(--stk) = 0xdeadbeef; /* r7 */
*(--stk) = 0xdeadbeef; /* r6 */
*(--stk) = 0xdeadbeef; /* r5 */
*(--stk) = 0xdeadbeef; /* r4 */
*(--stk) = 0xdeadbeef; /* r3 */
*(--stk) = 0xdeadbeef; /* r2 */
*(--stk) = 0xdeadbeef; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = Mode_SVC; /* cpsr */
*(--stk) = Mode_SVC; /* spsr */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

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RT_Thread/libcpu/arm/sep4020/start_rvds.S Normal file
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;==============================================================================================
; star_rvds.s for Keil MDK 4.10
;
; SEP4020 start up code
;
; Change Logs:
; Date Author Notes
; 2010-03-17 zchong
;=============================================================================================
PMU_PLTR EQU 0x10001000 ; PLL<4C><4C><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
PMU_PMCR EQU 0x10001004 ; ϵͳ<CFB5><CDB3>ʱ<EFBFBD><CAB1>PLL<4C>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
PMU_PUCR EQU 0x10001008 ; USBʱ<42><CAB1>PLL<4C>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
PMU_PCSR EQU 0x1000100C ; <20>ڲ<EFBFBD>ģ<EFBFBD><C4A3>ʱ<EFBFBD><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
PMU_PDSLOW EQU 0x10001010 ; SLOW״̬<D7B4><CCAC>ʱ<EFBFBD>ӵķ<D3B5>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>
PMU_PMDR EQU 0x10001014 ; оƬ<D0BE><C6AC><EFBFBD><EFBFBD>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD>
PMU_RCTR EQU 0x10001018 ; Reset<65><74><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
PMU_CLRWAKUP EQU 0x1000101C ; WakeUp<55><70><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
RTC_CTR EQU 0x1000200C ; RTC<54><43><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
INTC_IER EQU 0x10000000 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
INTC_IMR EQU 0x10000008 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>μĴ<CEBC><C4B4><EFBFBD>
INTC_IFSR EQU 0x10000030 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
INTC_FIER EQU 0x100000C0 ; FIQ<49>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
INTC_FIMR EQU 0x100000C4 ; FIQ<49>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>μĴ<CEBC><C4B4><EFBFBD>
EMI_CSACONF EQU 0x11000000 ; CSA<53><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
EMI_CSECONF EQU 0x11000010 ; CSE<53><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
EMI_CSFCONF EQU 0x11000014 ; CSF<53><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ<4D><CAB1><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>1
EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ<4D><CAB1><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>2, SDRAM<41><4D>ʼ<EFBFBD><CABC><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ<C6AC>ռ估<D5BC><E4BCB0>ַӳ<D6B7><D3B3>REMAP<41><50><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
NOINT EQU 0xc0
MASK_MODE EQU 0x0000003F
MODE_SVC32 EQU 0x00000013
; Internal Memory Base Addresses
FLASH_BASE EQU 0x20000000
RAM_BASE EQU 0x04000000
SDRAM_BASE EQU 0x30000000
; Stack
Unused_Stack_Size EQU 0x00000100
Svc_Stack_Size EQU 0x00001000
Abt_Stack_Size EQU 0x00000000
Fiq_Stack_Size EQU 0x00000000
Irq_Stack_Size EQU 0x00001000
Usr_Stack_Size EQU 0x00000000
;SVC STACK
AREA STACK, NOINIT, READWRITE, ALIGN=3
Svc_Stack SPACE Svc_Stack_Size
__initial_sp
Svc_Stack_Top
;IRQ STACK
AREA STACK, NOINIT, READWRITE, ALIGN=3
Irq_Stack SPACE Irq_Stack_Size
Irq_Stack_Top
;UNUSED STACK
AREA STACK, NOINIT, READWRITE, ALIGN=3
Unused_Stack SPACE Unused_Stack_Size
Unused_Stack_Top
; Heap
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT Heap_Mem
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
EXPORT Entry_Point
Entry_Point
Vectors LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP ; Reserved Vector
LDR PC,IRQ_Addr
LDR PC,FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B Abort_Handler
DAbt_Handler B Abort_Handler
FIQ_Handler B FIQ_Handler
Abort_Handler PROC
ARM
EXPORT Abort_Handler
DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
ENDP
; Reset Handler
;IMPORT __user_initial_stackheap
EXPORT Reset_Handler
Reset_Handler
;****************************************************************
;* Shutdown watchdog
;****************************************************************
LDR R0,=RTC_CTR
LDR R1,=0x0
STR R1,[R0]
;****************************************************************
;* shutdown interrupts
;****************************************************************
MRS R0, CPSR
BIC R0, R0, #MASK_MODE
ORR R0, R0, #MODE_SVC32
ORR R0, R0, #I_Bit
ORR R0, R0, #F_Bit
MSR CPSR_c, r0
LDR R0,=INTC_IER
LDR R1,=0x0
STR R1,[R0]
LDR R0,=INTC_IMR
LDR R1,=0xFFFFFFFF
STR R1,[R0]
LDR R0,=INTC_FIER
LDR R1,=0x0
STR R1,[R0]
LDR R0,=INTC_FIMR
LDR R1,=0x0F
STR R1,[R0]
;****************************************************************
;* Initialize Stack Pointer
;****************************************************************
LDR SP, =Svc_Stack_Top ;init SP_svc
MOV R4, #0xD2 ;chmod to irq and init SP_irq
MSR cpsr_c, R4
LDR SP, =Irq_Stack_Top
MOV R4, #0XD1 ;chomod to fiq and init SP_fiq
MSR cpsr_c, R4
LDR SP, =Unused_Stack_Top
MOV R4, #0XD7 ;chomod to abt and init SP_ABT
MSR cpsr_c, R4
LDR SP, =Unused_Stack_Top
MOV R4, #0XDB ;chomod to undf and init SP_UNDF
MSR cpsr_c, R4
LDR SP, =Unused_Stack_Top
;chomod to abt and init SP_sys
MOV R4, #0xDF ;all interrupts disabled
MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode
LDR SP, =Unused_Stack_Top
MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
MSR cpsr_c, R4
;****************************************************************
;* Initialize PMU & System Clock
;****************************************************************
LDR R4, =PMU_PCSR ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ʱ<EFBFBD><CAB1>
LDR R5, =0x0001ffff
STR R5, [ R4 ]
LDR R4, =PMU_PLTR ; <20><><EFBFBD><EFBFBD>PLL<4C>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ֵ50us*100M.
LDR R5, =0x00fa00fa
STR R5, [ R4 ]
LDR R4, =PMU_PMDR ; <20><>SLOWģʽ<C4A3><CABD><EFBFBD><EFBFBD>NORMALģʽ
LDR R5, =0x00000001
STR R5, [ R4 ]
LDR R4, =PMU_PMCR ; <20><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>Ϊ80MHz
LDR R5, =0x00004009 ; 400b -- 88M
STR R5, [ R4 ]
;PMU_PMCR<43>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>15λ<35><CEBB>Ҫ<EFBFBD>дӵ͵<D3B5><CDB5>ߵķ<DFB5>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>PLL<4C><4C>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LDR R4, =PMU_PMCR
LDR R5, =0x0000c009
STR R5, [ R4 ]
;****************************************************************
;* <20><>ʼ<EFBFBD><CABC>EMI
;****************************************************************
IF :DEF:INIT_EMI
LDR R4, =EMI_CSACONF ; CSAƬѡʱ<D1A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LDR R5, =0x08a6a6a1
STR R5, [ R4 ]
LDR R4, =EMI_CSECONF ; CSEƬѡʱ<D1A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><EFBFBD><EEB1A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LDR R5, =0x8cfffff1
STR R5, [ R4 ]
LDR R4, =EMI_SDCONF1 ; SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1
LDR R5, =0x1E104177
STR R5, [ R4 ]
LDR R4, =EMI_SDCONF2 ; SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
LDR R5, =0x80001860
STR R5, [ R4 ]
ENDIF
; Copy Exception Vectors to Internal RAM
IF :DEF:RAM_INTVEC
ADR R8, Vectors ; Source
LDR R9, =RAM_BASE ; Destination
LDMIA R8!, {R0-R7} ; Load Vectors
STMIA R9!, {R0-R7} ; Store Vectors
LDMIA R8!, {R0-R7} ; Load Handler Addresses
STMIA R9!, {R0-R7} ; Store Handler Addresses
ENDIF
; Remap on-chip RAM to address 0
IF :DEF:REMAP
LDR R0, =EMI_REMAPCONF
IF :DEF:RAM_INTVEC
MOV R1, #0x80000000
ELSE
MOV R1, #0x0000000b
ENDIF
STR R1, [R0, #0] ; Remap
ENDIF
;***************************************************************
;* Open irq interrupt
;***************************************************************
MRS R4, cpsr
BIC R4, R4, #0x80 ; set bit7 to zero
MSR cpsr_c, R4
; Enter the C code
IMPORT __main
LDR R0,=__main
BX R0
IMPORT rt_interrupt_enter
IMPORT rt_interrupt_leave
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_hw_trap_irq
IRQ_Handler PROC
EXPORT IRQ_Handler
STMFD sp!, {r0-r12,lr}
BL rt_interrupt_enter
BL rt_hw_trap_irq
BL rt_interrupt_leave
; if rt_thread_switch_interrupt_flag set, jump to
; rt_hw_context_switch_interrupt_do and don't return
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #1
BEQ rt_hw_context_switch_interrupt_do
LDMFD sp!, {r0-r12,lr}
SUBS pc, lr, #4
ENDP
; /*
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
; */
rt_hw_context_switch_interrupt_do PROC
EXPORT rt_hw_context_switch_interrupt_do
MOV r1, #0 ; clear flag
STR r1, [r0]
LDMFD sp!, {r0-r12,lr}; reload saved registers
STMFD sp!, {r0-r3} ; save r0-r3
MOV r1, sp
ADD sp, sp, #16 ; restore sp
SUB r2, lr, #4 ; save old task's pc to r2
MRS r3, spsr ; get cpsr of interrupt thread
; switch to SVC mode and no interrupt
MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC
STMFD sp!, {r2} ; push old task's pc
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
MOV r4, r1 ; Special optimised code below
MOV r5, r3
LDMFD r4!, {r0-r3}
STMFD sp!, {r0-r3} ; push old task's r3-r0
STMFD sp!, {r5} ; push old task's cpsr
MRS r4, spsr
STMFD sp!, {r4} ; push old task's spsr
LDR r4, =rt_interrupt_from_thread
LDR r5, [r4]
STR sp, [r5] ; store sp in preempted tasks's TCB
LDR r6, =rt_interrupt_to_thread
LDR r6, [r6]
LDR sp, [r6] ; get new task's stack pointer
LDMFD sp!, {r4} ; pop new task's spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task's psr
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
ENDP
ALIGN
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
EXPORT __initial_sp
ELSE ;__MICROLIB
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Svc_Stack + Svc_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Svc_Stack
BX LR
ALIGN
ENDIF
END

167
RT_Thread/libcpu/arm/sep4020/trap.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2006-05-27 Bernard add skyeye support
* 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include <sep4020.h>
/**
* @addtogroup S3C24X0
*/
/*@{*/
extern struct rt_thread *rt_current_thread;
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register (struct rt_hw_register *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
* When ARM7TDMI comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
rt_hw_cpu_shutdown();
}
/**
* The software interrupt instruction (SWI) is used for entering
* Supervisor mode, usually to request a particular supervisor
* function.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during an instruction prefetch.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during a data access.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
rt_hw_cpu_shutdown();
}
/**
* Normally, system will never reach here
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc isr_table[];
void rt_hw_trap_irq(void)
{
unsigned long intstat;
rt_uint32_t irq = 0;
rt_isr_handler_t isr_func;
void *param;
/*Get the final intrrupt source*/
intstat = *(RP)(INTC_IFSR);;
/*Shift to get the intrrupt number*/
while(intstat != 1)
{
intstat = intstat >> 1;
irq++;
}
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
}
void rt_hw_trap_fiq(void)
{
rt_kprintf("fast interrupt request\n");
}
/*@}*/