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冯佳
2025-06-19 21:56:46 +08:00
parent fe98e5f010
commit a4841450cf
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15
RT_Thread/libcpu/avr32/SConscript Normal file
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# RT-Thread building script for bridge
import os
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
group = []
list = os.listdir(cwd)
# cpu porting code files
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
Return('group')

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RT_Thread/libcpu/avr32/uc3/SConscript Normal file
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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

93
RT_Thread/libcpu/avr32/uc3/context_gcc.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-27 Kyle First version
*/
#define AVR32_SR 0
#define AVR32_SR_GM_OFFSET 16
.text
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
ssrf AVR32_SR_GM_OFFSET
mov pc, lr
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
csrf AVR32_SR_GM_OFFSET
mov pc, lr
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/*
* r8 --> from
* r9 --> to
*/
.globl rt_hw_context_switch
.type rt_hw_context_switch, %function
rt_hw_context_switch:
ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
stm --sp, r8-r12, lr /* Push R8-R12, LR */
st.w --sp, lr /* Push LR (instead of PC) */
mfsr r8, AVR32_SR /* Read Status Register */
cbr r8, AVR32_SR_GM_OFFSET /* Clear GM bit */
st.w --sp, r8 /* Push SR */
stm --sp, r0-r7 /* Push R0-R7 */
/* Stack layout: R8-R12, LR, PC, SR, R0-R7 */
st.w r12[0], sp /* Store SP in preempted tasks TCB */
ld.w sp, r11[0] /* Get new task stack pointer */
ldm sp++, r0-r7 /* pop R0-R7 */
ld.w r8, sp++ /* pop SR */
mtsr AVR32_SR, r8 /* Restore SR */
ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume to thread */
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* r0 --> to
*/
.globl rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function
rt_hw_context_switch_to:
ld.w sp, r12[0] /* Get new task stack pointer */
ldm sp++, r0-r7 /* pop R0-R7 */
ld.w r8, sp++ /* pop SR */
mtsr AVR32_SR, r8 /* Restore SR */
ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume execution */
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
.type rt_hw_context_switch_interrupt, %function
rt_hw_context_switch_interrupt:
lda.w r8, rt_thread_switch_interrupt_flag
ld.w r9, r8[0]
cp.w r9, 1
breq _reswitch
mov r9, 1
st.w r8[0], r9
lda.w r8, rt_interrupt_from_thread
st.w r8[0], r12
_reswitch:
lda.w r8, rt_interrupt_to_thread
st.w r8[0], r11
mov pc, lr

20
RT_Thread/libcpu/avr32/uc3/cpu.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
*/
#include <rtthread.h>
/**
* @addtogroup AVR32UC3
*/
/*@{*/
/*@}*/

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RT_Thread/libcpu/avr32/uc3/exception_gcc.S Normal file
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/**
* \file
*
* \brief Exception and interrupt vectors mapping for the INTC Software Driver.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#if !__AVR32_UC__ && !__AVR32_AP__
#error Implementation for the AVR32 architecture only.
#endif
#include <avr32/io.h>
//! @{
//! \verbatim
.section .exception, "ax", @progbits
// Start of Exception Vector Table.
/*
* EVBA must be aligned with a power of two strictly greater than the
* EVBA-relative offset of the last vector.
*/
.balign 0x200
// Export symbol.
.global _evba
.type _evba, @function
_evba:
.org 0x000
// Unrecoverable Exception.
_handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit.
_handle_TLB_Multiple_Hit:
rjmp $
.org 0x008
// Bus Error Data Fetch.
_handle_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
// Bus Error Instruction Fetch.
_handle_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
// NMI.
_handle_NMI:
rjmp $
.org 0x014
// Instruction Address.
_handle_Instruction_Address:
rjmp $
.org 0x018
// ITLB Protection.
_handle_ITLB_Protection:
rjmp $
.org 0x01C
// Breakpoint.
_handle_Breakpoint:
rjmp $
.org 0x020
// Illegal Opcode.
_handle_Illegal_Opcode:
rjmp $
.org 0x024
// Unimplemented Instruction.
_handle_Unimplemented_Instruction:
rjmp $
.org 0x028
// Privilege Violation.
_handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
_handle_Floating_Point:
rjmp $
.org 0x030
// Coprocessor Absent: UNUSED IN AVR32UC.
_handle_Coprocessor_Absent:
rjmp $
.org 0x034
// Data Address (Read).
_handle_Data_Address_Read:
rjmp $
.org 0x038
// Data Address (Write).
_handle_Data_Address_Write:
rjmp $
.org 0x03C
// DTLB Protection (Read).
_handle_DTLB_Protection_Read:
rjmp $
.org 0x040
// DTLB Protection (Write).
_handle_DTLB_Protection_Write:
rjmp $
.org 0x044
// DTLB Modified: UNUSED IN AVR32UC.
_handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read).
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write).
_handle_DTLB_Miss_Write:
rjmp $
.org 0x100
// Supervisor Call.
_handle_Supervisor_Call:
rjmp $
/*
* Interrupt support.
* The interrupt controller must provide the offset address relative to EVBA.
* Important note:
* All interrupts call a C function named _get_interrupt_handler.
* This function will read group and interrupt line number to then return in
*R12 a pointer to a user-provided interrupt handler.
*/
.balign 4
.irp priority, 0, 1, 2, 3
.global _int\priority
.type _int\priority, @function
_int\priority:
#if __AVR32_UC__
/*
* R8-R12, LR, PC and SR are automatically pushed onto the system stack
* by the CPU upon interrupt entry. No other register is saved by
* hardware.
*/
#elif __AVR32_AP__
/*
* PC and SR are automatically saved in respectively RAR_INTx and
* RSR_INTx by the CPU upon interrupt entry. No other register is saved
* by hardware.
*/
pushm r8-r12, lr
#endif
mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
breq _spint\priority // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
call rt_interrupt_enter
icall r12
call rt_interrupt_leave
ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
ld.w r11, r12[0]
cp.w r11, 0
brne _spint\priority
lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
ld.w r11, r12[0]
cp.w r11, 1
breq rt_hw_context_switch_interrupt_do
_spint\priority:
csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
#if __AVR32_UC__
/*
* If this was not a spurious interrupt (R12 != NULL), jump to the
* handler.
*/
/* movne pc, r12 */
#elif __AVR32_AP__
// If this was a spurious interrupt (R12 == NULL), branch.
breq spint\priority
/*
* Push the pointer to the interrupt handler onto the system stack since
* no register may be altered.
*/
st.w --sp, r12
popm r8-r12, lr, pc // Restore registers and jump to the handler.
spint\priority:
popm r8-r12, lr
#endif
/*
* If this was a spurious interrupt (R12 == NULL), return from event
* handler.
*/
rete
.endr
rt_hw_context_switch_interrupt_do:
mov r11, 0
st.w r12[0], r11 /* Clear rt_thread_switch_interrupt_flag */
stm --sp, r0-r7 /* Push R0-R7 */
lda.w r12, rt_interrupt_from_thread /* Get old thread SP */
ld.w r12, r12[0]
lda.w r11, rt_interrupt_to_thread /* Get new thread SP */
ld.w r11, r11[0]
st.w r12[0], sp /* Store old thread SP */
ld.w sp, r11[0] /* Load new thread SP */
ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */
rete /* RETE pops R8-R12, LR, PC, SR automatically */
// Constant data area.
.balign 4
// Values to store in the interrupt priority registers for the various interrupt priority levels.
// The interrupt priority registers contain the interrupt priority level and
// the EVBA-relative interrupt vector offset.
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
//! \endverbatim
//! @}

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RT_Thread/libcpu/avr32/uc3/interrupt.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle Ported from STM32 to AVR32.
*/
#include <rtthread.h>
#include "compiler.h"
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;

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RT_Thread/libcpu/avr32/uc3/stack.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
*/
#include <rtthread.h>
/**
* @addtogroup AVR32UC3
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
unsigned long *stk;
stk = (unsigned long *)stack_addr;
*(stk) = 0; /* r8 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r12 */
*(--stk) = (unsigned long)texit; /* lr */
*(--stk) = (unsigned long)tentry; /* entry point, pc */
*(--stk) = 0x00600000; /* sr */
*(--stk) = 0; /* r0 */
*(--stk) = 0; /* r1 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r4 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r7 */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/