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冯佳
2025-06-19 21:56:46 +08:00
parent fe98e5f010
commit a4841450cf
4152 changed files with 1910684 additions and 0 deletions
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13
RT_Thread/libcpu/m16c/m16c62p/SConscript Normal file
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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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RT_Thread/libcpu/m16c/m16c62p/context_gcc.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
*/
.section .text
.globl _rt_interrupt_from_thread
.globl _rt_interrupt_to_thread
.global _os_context_switch
.type _os_context_switch, @function
_os_context_switch:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB
MOV.W _rt_interrupt_from_thread, A0
STC ISP, [A0]
MOV.W _rt_interrupt_to_thread, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
REIT ; Return from interrup
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* this fucntion is used to perform the first thread switch
*/
.global _rt_hw_context_switch_to
.type _rt_hw_context_switch_to, @function
_rt_hw_context_switch_to:
ENTER #0x0
MOV.W 0x5[FB], A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB
REIT
.end

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RT_Thread/libcpu/m16c/m16c62p/context_iar.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
*/
RSEG CSTACK
RSEG ISTACK
RSEG CODE(1)
EXTERN rt_interrupt_from_thread
EXTERN rt_interrupt_to_thread
PUBLIC rt_hw_interrupt_disable
PUBLIC rt_hw_interrupt_enable
PUBLIC rt_hw_context_switch_to
PUBLIC os_context_switch
rt_hw_interrupt_disable:
STC FLG, R0 ;fify 20100419
FCLR I
RTS
rt_hw_interrupt_enable:
LDC R0, FLG ;fify 20100419
RTS
.EVEN
os_context_switch:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB
MOV.W rt_interrupt_from_thread, A0
STC ISP, [A0]
MOV.W rt_interrupt_to_thread, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
REIT ; Return from interrup
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
* this fucntion is used to perform the first thread switch
*/
rt_hw_context_switch_to:
MOV.W R0, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB
REIT
END

59
RT_Thread/libcpu/m16c/m16c62p/context_iar.asm Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
*/
RSEG CSTACK
RSEG ISTACK
RSEG CODE(1)
EXTERN rt_interrupt_from_thread
EXTERN rt_interrupt_to_thread
PUBLIC rt_hw_interrupt_disable
PUBLIC rt_hw_interrupt_enable
PUBLIC rt_hw_context_switch_to
PUBLIC os_context_switch
rt_hw_interrupt_disable:
STC FLG, R0 ;fify 20100419
FCLR I
RTS
rt_hw_interrupt_enable:
LDC R0, FLG ;fify 20100419
RTS
.EVEN
os_context_switch:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB
MOV.W rt_interrupt_from_thread, A0
STC ISP, [A0]
MOV.W rt_interrupt_to_thread, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
REIT ; Return from interrup
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
* this fucntion is used to perform the first thread switch
*/
rt_hw_context_switch_to:
MOV.W R0, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB
REIT
END

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RT_Thread/libcpu/m16c/m16c62p/cpuport.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-02-23 Bernard the first version
* 2012-09-25 lgnq save texit address in to thread stack
*/
#include <rtthread.h>
extern volatile rt_atomic_t rt_interrupt_nest;
/* switch flag on interrupt and thread pointer to save switch record */
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint8_t rt_thread_switch_interrupt_flag;
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry,
void *parameter,
rt_uint8_t *stack_addr,
void *texit)
{
rt_uint16_t *pstk16;
rt_uint16_t flag;
flag = 0x0040;
pstk16 = (rt_uint16_t *)stack_addr;
*pstk16-- = (rt_uint32_t)texit >> 16L;
*pstk16-- = (rt_uint32_t)texit & 0x0000FFFFL;
/* Simulate ISR entry */
*pstk16-- = (flag&0x00FF) | /* The lowest byte of the FLAG register */
(((rt_uint32_t)tentry>>8)&0x00000F00) | /* The highest nibble of the PC register */
((flag<<4)&0xF000); /* The highest nibble of the FLAG register */
*pstk16-- = (((rt_uint32_t)tentry)&0x0000FFFF); /* The lowest bytes of the PC register */
/* Save registers onto stack frame */
*pstk16-- = (rt_uint16_t)0xFBFB; /* FB register */
*pstk16-- = (rt_uint16_t)0x3B3B; /* SB register */
*pstk16-- = (rt_uint16_t)0xA1A1; /* A1 register */
*pstk16-- = (rt_uint16_t)0xA0A0; /* A0 register */
*pstk16-- = (rt_uint16_t)0x3333; /* R3 register */
*pstk16-- = (rt_uint32_t)parameter >> 16L; /* Pass argument in R2 register */
*pstk16-- = (rt_uint32_t)parameter & 0x0000FFFFL; /* Pass argument in R1 register */
*pstk16 = (rt_uint16_t)0x0000; /* R0 register */
/* return task's current stack address */
return (rt_uint8_t *)pstk16;
}
void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
{
rt_interrupt_from_thread = from;
rt_interrupt_to_thread = to;
asm("INT #0");
}
void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
{
if (rt_thread_switch_interrupt_flag != 1)
{
rt_thread_switch_interrupt_flag = 1;
rt_interrupt_from_thread = from;
}
rt_interrupt_to_thread = to;
}
#if defined(__GNUC__)
rt_base_t rt_hw_interrupt_disable(void)
{
register rt_uint16_t temp;
asm("STC FLG, %0":"=r" (temp));
asm("FCLR I");
return (rt_base_t)temp;
}
void rt_hw_interrupt_enable(rt_base_t level)
{
register rt_uint16_t temp;
temp = level & 0xffff;
asm("LDC %0, FLG": :"r" (temp));
}
#endif