原始版本
This commit is contained in:
冯佳
13
RT_Thread/libcpu/mips/gs232/SConscript
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13
RT_Thread/libcpu/mips/gs232/SConscript
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@ -0,0 +1,13 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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231
RT_Thread/libcpu/mips/gs232/cache.c
Normal file
231
RT_Thread/libcpu/mips/gs232/cache.c
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@ -0,0 +1,231 @@
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/*
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* Cache Ops For Loongson GS232
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*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2011-08-08 lgnq modified for LS1B
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* 2015-07-08 chinesebear modified for loongson 1c
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*/
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#include <rtthread.h>
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#include <mips.h>
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#define K0BASE 0x80000000
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#define PRID_LS1C 0x4220
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extern void Clear_TagLo (void);
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extern void Invalidate_Icache_Ls1c(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void enable_cpu_cache(void);
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typedef struct cacheinfo_t
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{
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unsigned int icache_size;
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unsigned int dcache_size;
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unsigned int icacheline_size;
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unsigned int dcacheline_size;
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} cacheinfo_t ;
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typedef struct cacheop_t
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{
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void (*Clear_TagLo) (void);
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void (*Invalidate_Icache) (unsigned int);
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void (*Invalidate_Dcache_Fill) (unsigned int);
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void (*Invalidate_Dcache_ClearTag) (unsigned int);
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void (*Init_Cache)(void);
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} cacheop_t ;
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static cacheop_t cacheop, *pcacheop;
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static cacheinfo_t cacheinfo, *pcacheinfo;
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int identify_cpu(void)
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{
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unsigned int cpu_id;
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pcacheop = &cacheop;
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pcacheinfo = &cacheinfo;
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rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
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cpu_id = read_c0_prid();
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switch (cpu_id)
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{
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case PRID_LS1C:
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rt_kprintf("CPU:Loongson 1C\n");
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pcacheop->Clear_TagLo = Clear_TagLo;
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pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
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pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
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pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
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break;
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default:
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rt_kprintf("Unknown CPU type, system halted!\n");
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while (1)
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{
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;
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}
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break;
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}
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return 0;
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}
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void probe_cache(void)
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{
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unsigned int config1 = read_c0_config1();
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unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
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unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
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if ((icache_line_size = ((config1 >> 19) & 7)))
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icache_line_size = 2 << icache_line_size;
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else
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icache_line_size = icache_line_size;
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icache_sets = 64 << ((config1 >> 22) & 7);
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icache_ways = 1 + ((config1 >> 16) & 7);
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icache_size = icache_sets * icache_ways * icache_line_size;
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if ((dcache_line_size = ((config1 >> 10) & 7)))
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dcache_line_size = 2 << dcache_line_size;
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else
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dcache_line_size = dcache_line_size;
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dcache_sets = 64 << ((config1 >> 13) & 7);
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dcache_ways = 1 + ((config1 >> 7) & 7);
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dcache_size = dcache_sets * dcache_ways * dcache_line_size;
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rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
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rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
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pcacheinfo->icache_size = icache_size;
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pcacheinfo->dcache_size = dcache_size;
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pcacheinfo->icacheline_size = icache_line_size;
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pcacheinfo->dcacheline_size = dcache_line_size;
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return ;
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}
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void invalidate_writeback_dcache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start < end)
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{
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Writeback_Invalidate_Dcache(start); //hit writeback invalidate
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start += pcacheinfo->dcacheline_size;
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}
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}
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void invalidate_writeback_dcache(unsigned long addr, int size)
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{
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unsigned long start, end;
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start = (addr + pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
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end = (addr + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
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while (start <end)
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{
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Writeback_Invalidate_Dcache(start);
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start += pcacheinfo->dcacheline_size;
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}
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}
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void invalidate_icache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->icache_size);
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while (start < end)
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{
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pcacheop->Invalidate_Icache(start);
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start += pcacheinfo->icacheline_size;
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}
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}
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void invalidate_dcache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start <end)
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{
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Invalidate_Dcache_Fill_Ls1c(start);
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start += pcacheinfo->icacheline_size;
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}
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}
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//with cache disabled
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void init_dcache(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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}
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void rt_hw_cache_init(void)
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{
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unsigned int start, end;
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/* 1. identify cpu and probe cache */
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identify_cpu();
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probe_cache();
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start = K0BASE;
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end = (start + pcacheinfo->icache_size);
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/*
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* 2. clear CP0 taglo/taghi register;
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*/
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pcacheop->Clear_TagLo();
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/*
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* 3. invalidate instruction cache;
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*/
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while (start < end)
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{
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pcacheop->Invalidate_Icache(start); //index invalidate icache
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start += pcacheinfo->icacheline_size;
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}
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/*
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* 4. invalidate data cache;
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*/
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start = K0BASE;
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end = (start + pcacheinfo->dcache_size);
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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start = K0BASE;
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
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start += pcacheinfo->dcacheline_size;
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}
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start = K0BASE;
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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/* enable cache */
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enable_cpu_cache();
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rt_kprintf("enable cpu cache done\n");
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return ;
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}
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51
RT_Thread/libcpu/mips/gs232/cache.h
Normal file
51
RT_Thread/libcpu/mips/gs232/cache.h
Normal file
@ -0,0 +1,51 @@
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/*
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* Cache Ops For Loongson GS232
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*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2011-08-08 lgnq modified for LS1B
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* 2015-07-08 chinesebear modified for loongson 1c
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*/
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#ifndef __CACHE_H__
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#define __CACHE_H__
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/*
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* Cache Operations
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_D 0x0d
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#define Create_Dirty_Excl_SD 0x0f
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Fill 0x14
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#define Hit_Writeback_Inv_D 0x15
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/* 0x16 is unused */
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#define Hit_Writeback_Inv_SD 0x17
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#define Hit_Writeback_I 0x18
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#define Hit_Writeback_D 0x19
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/* 0x1a is unused */
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#define Hit_Writeback_SD 0x1b
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/* 0x1c is unused */
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/* 0x1e is unused */
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#define Hit_Set_Virtual_SI 0x1e
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#define Hit_Set_Virtual_SD 0x1f
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#endif
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218
RT_Thread/libcpu/mips/gs232/cache_gcc.S
Normal file
218
RT_Thread/libcpu/mips/gs232/cache_gcc.S
Normal file
@ -0,0 +1,218 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-17 swkyer first version
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* 2010-09-11 bernard port to Loongson SoC3210
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* 2011-08-08 lgnq port to Loongson LS1B
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* 2015-07-08 chinesebear port to Loongson LS1C
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* 2019-07-19 Zhou Yanjie clean up code
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <mips.h>
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#include "cache.h"
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.ent cache_init
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.global cache_init
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.set noreorder
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cache_init:
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move t1,ra
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####part 2####
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cache_detect_4way:
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mfc0 t4, CP0_CONFIG
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andi t5, t4, 0x0e00
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srl t5, t5, 9 #ic
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andi t6, t4, 0x01c0
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srl t6, t6, 6 #dc
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addiu t8, $0, 1
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addiu t9, $0, 2
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#set dcache way
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beq t6, $0, cache_d1way
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addiu t7, $0, 1 #1 way
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beq t6, t8, cache_d2way
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addiu t7, $0, 2 #2 way
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beq $0, $0, cache_d4way
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addiu t7, $0, 4 #4 way
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cache_d1way:
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beq $0, $0, 1f
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addiu t6, t6, 12 #1 way
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cache_d2way:
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beq $0, $0, 1f
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addiu t6, t6, 11 #2 way
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cache_d4way:
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addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
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1: #set icache way
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beq t5, $0, cache_i1way
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addiu t3, $0, 1 #1 way
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beq t5, t8, cache_i2way
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addiu t3, $0, 2 #2 way
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beq $0, $0, cache_i4way
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addiu t3, $0, 4 #4 way
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cache_i1way:
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beq $0, $0, 1f
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addiu t5, t5, 12
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cache_i2way:
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beq $0, $0, 1f
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addiu t5, t5, 11
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cache_i4way:
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addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
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1: addiu t4, $0, 1
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sllv t6, t4, t6
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sllv t5, t4, t5
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||||
#if 0
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la t0, memvar
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sw t7, 0x0(t0) #ways
|
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sw t5, 0x4(t0) #icache size
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sw t6, 0x8(t0) #dcache size
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||||
#endif
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||||
####part 3####
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||||
.set mips3
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||||
lui a0, 0x8000
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addu a1, $0, t5
|
||||
addu a2, $0, t6
|
||||
cache_init_d2way:
|
||||
#a0=0x80000000, a1=icache_size, a2=dcache_size
|
||||
#a3, v0 and v1 used as local registers
|
||||
mtc0 $0, CP0_TAGHI
|
||||
addu v0, $0, a0
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||||
addu v1, a0, a2
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||||
1: slt a3, v0, v1
|
||||
beq a3, $0, 1f
|
||||
nop
|
||||
mtc0 $0, CP0_TAGLO
|
||||
beq t7, 1, 4f
|
||||
cache Index_Store_Tag_D, 0x0(v0) # 1 way
|
||||
beq t7, 2 ,4f
|
||||
cache Index_Store_Tag_D, 0x1(v0) # 2 way
|
||||
cache Index_Store_Tag_D, 0x2(v0) # 4 way
|
||||
cache Index_Store_Tag_D, 0x3(v0)
|
||||
4: beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
1:
|
||||
cache_flush_i2way:
|
||||
addu v0, $0, a0
|
||||
addu v1, a0, a1
|
||||
1: slt a3, v0, v1
|
||||
beq a3, $0, 1f
|
||||
nop
|
||||
beq t3, 1, 4f
|
||||
cache Index_Invalidate_I, 0x0(v0) # 1 way
|
||||
beq t3, 2, 4f
|
||||
cache Index_Invalidate_I, 0x1(v0) # 2 way
|
||||
cache Index_Invalidate_I, 0x2(v0)
|
||||
cache Index_Invalidate_I, 0x3(v0) # 4 way
|
||||
4: beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
1:
|
||||
cache_flush_d2way:
|
||||
addu v0, $0, a0
|
||||
addu v1, a0, a2
|
||||
1: slt a3, v0, v1
|
||||
beq a3, $0, 1f
|
||||
nop
|
||||
beq t7, 1, 4f
|
||||
cache Index_Writeback_Inv_D, 0x0(v0) #1 way
|
||||
beq t7, 2, 4f
|
||||
cache Index_Writeback_Inv_D, 0x1(v0) # 2 way
|
||||
cache Index_Writeback_Inv_D, 0x2(v0)
|
||||
cache Index_Writeback_Inv_D, 0x3(v0) # 4 way
|
||||
4: beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
1:
|
||||
cache_init_finish:
|
||||
jr t1
|
||||
nop
|
||||
.set reorder
|
||||
.end cache_init
|
||||
|
||||
###########################
|
||||
# Enable CPU cache #
|
||||
###########################
|
||||
|
||||
LEAF(enable_cpu_cache)
|
||||
.set noreorder
|
||||
mfc0 t0, CP0_CONFIG
|
||||
nop
|
||||
and t0, ~0x03
|
||||
or t0, 0x03
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
.set reorder
|
||||
j ra
|
||||
END (enable_cpu_cache)
|
||||
|
||||
###########################
|
||||
# disable CPU cache #
|
||||
###########################
|
||||
|
||||
LEAF(disable_cpu_cache)
|
||||
.set noreorder
|
||||
mfc0 t0, CP0_CONFIG
|
||||
nop
|
||||
and t0, ~0x03
|
||||
or t0, 0x2
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
.set reorder
|
||||
j ra
|
||||
END (disable_cpu_cache)
|
||||
|
||||
/**********************************/
|
||||
/* Invalidate Instruction Cache */
|
||||
/**********************************/
|
||||
LEAF(Clear_TagLo)
|
||||
.set noreorder
|
||||
mtc0 zero, CP0_TAGLO
|
||||
nop
|
||||
.set reorder
|
||||
j ra
|
||||
END(Clear_TagLo)
|
||||
|
||||
.set mips3
|
||||
/**********************************/
|
||||
/* Invalidate Instruction Cache */
|
||||
/**********************************/
|
||||
LEAF(Invalidate_Icache_Ls1c)
|
||||
.set noreorder
|
||||
cache Index_Invalidate_I,0(a0)
|
||||
cache Index_Invalidate_I,1(a0)
|
||||
cache Index_Invalidate_I,2(a0)
|
||||
cache Index_Invalidate_I,3(a0)
|
||||
.set reorder
|
||||
j ra
|
||||
END(Invalidate_Icache_Ls1c)
|
||||
|
||||
/**********************************/
|
||||
/* Invalidate Data Cache */
|
||||
/**********************************/
|
||||
LEAF(Invalidate_Dcache_ClearTag_Ls1c)
|
||||
.set noreorder
|
||||
cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag
|
||||
cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag
|
||||
.set reorder
|
||||
j ra
|
||||
END(Invalidate_Dcache_ClearTag_Ls1c)
|
||||
|
||||
LEAF(Invalidate_Dcache_Fill_Ls1c)
|
||||
.set noreorder
|
||||
cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag
|
||||
cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag
|
||||
.set reorder
|
||||
j ra
|
||||
END(Invalidate_Dcache_Fill_Ls1c)
|
||||
|
||||
LEAF(Writeback_Invalidate_Dcache)
|
||||
.set noreorder
|
||||
cache Hit_Writeback_Inv_D, (a0)
|
||||
.set reorder
|
||||
j ra
|
||||
END(Writeback_Invalidate_Dcache)
|
||||
.set mips0
|
||||
23
RT_Thread/libcpu/mips/gs232/cpuinit_gcc.S
Normal file
23
RT_Thread/libcpu/mips/gs232/cpuinit_gcc.S
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include <mips.h>
|
||||
|
||||
.section ".start", "ax"
|
||||
.set noreorder
|
||||
|
||||
.globl rt_cpu_early_init
|
||||
rt_cpu_early_init:
|
||||
jr ra
|
||||
nop
|
||||
60
RT_Thread/libcpu/mips/gs232/cpuport.c
Normal file
60
RT_Thread/libcpu/mips/gs232/cpuport.c
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-07-09 Bernard first version
|
||||
* 2010-09-11 Bernard add CPU reset implementation
|
||||
* 2015-07-06 chinesebear modified for loongson 1c
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "gs232.h"
|
||||
|
||||
/**
|
||||
* @addtogroup Loongson GS232
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* this function will reset CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset(void)
|
||||
{
|
||||
/* open the watch-dog */
|
||||
WDT_EN = 0x01; /* watch dog enable */
|
||||
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
|
||||
WDT_SET = 0x01; /* watch dog start */
|
||||
|
||||
rt_kprintf("reboot system...\n");
|
||||
while (1);
|
||||
}
|
||||
|
||||
#define Hit_Invalidate_I 0x10
|
||||
#define Hit_Invalidate_D 0x11
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define Hit_Writeback_Inv_D 0x15
|
||||
|
||||
|
||||
void flush_cache(unsigned long start_addr, unsigned long size)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
|
||||
|
||||
while (1) {
|
||||
cache_op(Hit_Writeback_Inv_D, addr);
|
||||
cache_op(Hit_Invalidate_I, addr);
|
||||
if (addr == aend)
|
||||
break;
|
||||
addr += lsize;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*@}*/
|
||||
|
||||
74
RT_Thread/libcpu/mips/gs232/gs232.h
Normal file
74
RT_Thread/libcpu/mips/gs232/gs232.h
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Misc define for GS232
|
||||
*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#ifndef __GS232_H__
|
||||
#define __GS232_H__
|
||||
|
||||
#include <mips.h>
|
||||
|
||||
#define INTC_BASE 0xBFD01040
|
||||
|
||||
#ifdef SOC_LS1B
|
||||
#define GS232_INTC_CELLS 4
|
||||
#endif
|
||||
|
||||
#ifdef SOC_LS1C300
|
||||
#define GS232_INTC_CELLS 5
|
||||
#endif
|
||||
|
||||
#define GS232_NR_IRQS (32 * GS232_INTC_CELLS)
|
||||
|
||||
#define GMAC0_BASE 0xBFE10000
|
||||
#define GMAC0_DMA_BASE 0xBFE11000
|
||||
#define GMAC1_BASE 0xBFE20000
|
||||
#define GMAC1_DMA_BASE 0xBFE21000
|
||||
#define I2C0_BASE 0xBFE58000
|
||||
#define PWM0_BASE 0xBFE5C000
|
||||
#define PWM1_BASE 0xBFE5C010
|
||||
#define PWM2_BASE 0xBFE5C020
|
||||
#define PWM3_BASE 0xBFE5C030
|
||||
#define WDT_BASE 0xBFE5C060
|
||||
#define RTC_BASE 0xBFE64000
|
||||
#define I2C1_BASE 0xBFE68000
|
||||
#define I2C2_BASE 0xBFE70000
|
||||
#define AC97_BASE 0xBFE74000
|
||||
#define NAND_BASE 0xBFE78000
|
||||
#define SPI_BASE 0xBFE80000
|
||||
#define CAN1_BASE 0xBF004300
|
||||
#define CAN0_BASE 0xBF004400
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <rthw.h>
|
||||
|
||||
/* Watch Dog registers */
|
||||
#define WDT_EN HWREG32(WDT_BASE + 0x00)
|
||||
#define WDT_SET HWREG32(WDT_BASE + 0x08)
|
||||
#define WDT_TIMER HWREG32(WDT_BASE + 0x04)
|
||||
|
||||
#define PLL_FREQ HWREG32(0xbfe78030)
|
||||
#define PLL_DIV_PARAM HWREG32(0xbfe78034)
|
||||
|
||||
struct gs232_intc_regs
|
||||
{
|
||||
volatile unsigned int int_isr;
|
||||
volatile unsigned int int_en;
|
||||
volatile unsigned int int_set;
|
||||
volatile unsigned int int_clr; /* offset 0x10*/
|
||||
volatile unsigned int int_pol;
|
||||
volatile unsigned int int_edge; /* offset 0 */
|
||||
};
|
||||
|
||||
extern void rt_hw_timer_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
161
RT_Thread/libcpu/mips/gs232/interrupt.c
Normal file
161
RT_Thread/libcpu/mips/gs232/interrupt.c
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Interrupt handle for GS232
|
||||
*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-10-15 Bernard first version
|
||||
* 2010-10-15 lgnq modified for LS1B
|
||||
* 2013-03-29 aozima Modify the interrupt interface implementations.
|
||||
* 2015-07-06 chinesebear modified for loongson 1c
|
||||
* 2019-12-04 Jiaxun Yang Generialize
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include "gs232.h"
|
||||
|
||||
|
||||
#define MAX_INTR (GS232_NR_IRQS)
|
||||
|
||||
static struct rt_irq_desc irq_handle_table[MAX_INTR];
|
||||
void rt_hw_timer_handler();
|
||||
|
||||
static struct gs232_intc_regs volatile *gs232_hw0_icregs
|
||||
= (struct gs232_intc_regs volatile *)(INTC_BASE);
|
||||
|
||||
/**
|
||||
* @addtogroup Loongson GS232
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
static void rt_hw_interrupt_handler(int vector, void *param)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_int32_t idx;
|
||||
rt_int32_t i;
|
||||
rt_uint32_t c0_status = 0;
|
||||
|
||||
for (i=0; i < GS232_INTC_CELLS; i++)
|
||||
{
|
||||
/* Disable */
|
||||
(gs232_hw0_icregs+i)->int_en = 0x0;
|
||||
/* Trigger active low */
|
||||
(gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */
|
||||
/* Make all interrupts level triggered */
|
||||
(gs232_hw0_icregs+i)->int_edge = 0x00000000;
|
||||
/* Mask all interrupts */
|
||||
(gs232_hw0_icregs+i)->int_clr = 0xffffffff;
|
||||
mips_unmask_cpu_irq(i + 2);
|
||||
}
|
||||
|
||||
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
|
||||
for (idx = 0; idx < MAX_INTR; idx ++)
|
||||
{
|
||||
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* mask interrupt */
|
||||
(gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
(gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if (vector >= 0 && vector < MAX_INTR)
|
||||
{
|
||||
old_handler = irq_handle_table[vector].handler;
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
irq_handle_table[vector].handler = handler;
|
||||
irq_handle_table[vector].param = param;
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Call ISR
|
||||
* @IRQn ID of IRQ
|
||||
*/
|
||||
void gs232_do_IRQ(int IRQn)
|
||||
{
|
||||
rt_isr_handler_t irq_func;
|
||||
void *param;
|
||||
|
||||
irq_func = irq_handle_table[IRQn].handler;
|
||||
param = irq_handle_table[IRQn].param;
|
||||
|
||||
irq_func(IRQn, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
irq_handle_table[IRQn].counter++;
|
||||
#endif
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
void rt_do_mips_cpu_irq(rt_uint32_t ip)
|
||||
{
|
||||
rt_uint32_t intstatus, irq, n;
|
||||
|
||||
if (ip == 7) {
|
||||
rt_hw_timer_handler();
|
||||
} else {
|
||||
n = ip - 2;
|
||||
/* Receive interrupt signal, compute the irq */
|
||||
intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en;
|
||||
if (0 == intstatus)
|
||||
return ;
|
||||
|
||||
irq = __rt_ffs(intstatus) - 1;
|
||||
gs232_do_IRQ((n<<5) + irq);
|
||||
|
||||
/* ack interrupt */
|
||||
(gs232_hw0_icregs+n)->int_clr |= (1 << irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
76
RT_Thread/libcpu/mips/gs232/ls1b.h
Normal file
76
RT_Thread/libcpu/mips/gs232/ls1b.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-08-08 lgnq first version
|
||||
*/
|
||||
|
||||
#ifndef __LS1B_H__
|
||||
#define __LS1B_H__
|
||||
|
||||
#include <gs232.h>
|
||||
|
||||
#define LS1B_ACPI_IRQ 0
|
||||
#define LS1B_HPET_IRQ 1
|
||||
#define LS1B_UART0_IRQ 2
|
||||
#define LS1B_UART1_IRQ 3
|
||||
#define LS1B_UART2_IRQ 4
|
||||
#define LS1B_UART3_IRQ 5
|
||||
#define LS1B_UART4_IRQ 29
|
||||
#define LS1B_UART5_IRQ 30
|
||||
#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ
|
||||
#define LS1B_UART7_IRQ 2
|
||||
#define LS1B_UART8_IRQ 2
|
||||
#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ
|
||||
#define LS1B_UART10_IRQ 3
|
||||
#define LS1B_UART11_IRQ 3
|
||||
|
||||
#define LS1B_CAN0_IRQ 6
|
||||
#define LS1B_CAN1_IRQ 7
|
||||
#define LS1B_SPI0_IRQ 8
|
||||
#define LS1B_SPI1_IRQ 9
|
||||
#define LS1B_AC97_IRQ 10
|
||||
#define LS1B_MS_IRQ 11
|
||||
#define LS1B_KB_IRQ 12
|
||||
#define LS1B_DMA0_IRQ 13
|
||||
#define LS1B_DMA1_IRQ 14
|
||||
#define LS1B_NAND_IRQ 15
|
||||
#define LS1B_I2C0_IRQ 16
|
||||
#define LS1B_I2C1_IRQ 17
|
||||
#define LS1B_PWM0_IRQ 18
|
||||
#define LS1B_PWM1_IRQ 19
|
||||
#define LS1B_PWM2_IRQ 20
|
||||
#define LS1B_PWM3_IRQ 21
|
||||
#define LS1B_LPC_IRQ 22
|
||||
#define LS1B_EHCI_IRQ 32
|
||||
#define LS1B_OHCI_IRQ 33
|
||||
#define LS1B_GMAC1_IRQ 34
|
||||
#define LS1B_GMAC2_IRQ 35
|
||||
#define LS1B_SATA_IRQ 36
|
||||
#define LS1B_GPU_IRQ 37
|
||||
#define LS1B_PCI_INTA_IRQ 38
|
||||
#define LS1B_PCI_INTB_IRQ 39
|
||||
#define LS1B_PCI_INTC_IRQ 40
|
||||
#define LS1B_PCI_INTD_IRQ 41
|
||||
|
||||
#define LS1B_GPIO_IRQ 64
|
||||
#define LS1B_GPIO_FIRST_IRQ 64
|
||||
#define LS1B_GPIO_IRQ_COUNT 64
|
||||
#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
|
||||
|
||||
#define INT_PCI_INTA (1<<6)
|
||||
#define INT_PCI_INTB (1<<7)
|
||||
#define INT_PCI_INTC (1<<8)
|
||||
#define INT_PCI_INTD (1<<9)
|
||||
|
||||
#define LS1B_LAST_IRQ 159
|
||||
#define MIPS_CPU_TIMER_IRQ 167
|
||||
#define LS1B_INTREG_BASE 0xbfd01040
|
||||
|
||||
#define LS1B_DMA_IRQ_BASE 168
|
||||
#define LS1B_DMA_IRQ_COUNT 16
|
||||
|
||||
#endif
|
||||
81
RT_Thread/libcpu/mips/gs232/ls1c.h
Normal file
81
RT_Thread/libcpu/mips/gs232/ls1c.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-08-08 lgnq first version
|
||||
* 2015-07-06 chinesebear modified for loongson 1c
|
||||
*/
|
||||
|
||||
#ifndef __LS1C_H__
|
||||
#define __LS1C_H__
|
||||
|
||||
#include <gs232.h>
|
||||
|
||||
#define LS1C_ACPI_IRQ 0
|
||||
#define LS1C_HPET_IRQ 1
|
||||
//#define LS1C_UART0_IRQ 3 // linux使用3，v1.4版本之前1c分配有问题，建议使用2，以确保正确
|
||||
#define LS1C_UART1_IRQ 4
|
||||
#define LS1C_UART2_IRQ 5
|
||||
#define LS1C_CAN0_IRQ 6
|
||||
#define LS1C_CAN1_IRQ 7
|
||||
#define LS1C_SPI0_IRQ 8
|
||||
#define LS1C_SPI1_IRQ 9
|
||||
#define LS1C_AC97_IRQ 10
|
||||
#define LS1C_MS_IRQ 11
|
||||
#define LS1C_KB_IRQ 12
|
||||
#define LS1C_DMA0_IRQ 13
|
||||
#define LS1C_DMA1_IRQ 14
|
||||
#define LS1C_DMA2_IRQ 15
|
||||
#define LS1C_NAND_IRQ 16
|
||||
#define LS1C_PWM0_IRQ 17
|
||||
#define LS1C_PWM1_IRQ 18
|
||||
#define LS1C_PWM2_IRQ 19
|
||||
#define LS1C_PWM3_IRQ 20
|
||||
#define LS1C_RTC_INT0_IRQ 21
|
||||
#define LS1C_RTC_INT1_IRQ 22
|
||||
#define LS1C_RTC_INT2_IRQ 23
|
||||
#define LS1C_UART3_IRQ 29
|
||||
#define LS1C_ADC_IRQ 30
|
||||
#define LS1C_SDIO_IRQ 31
|
||||
|
||||
|
||||
#define LS1C_EHCI_IRQ (32+0)
|
||||
#define LS1C_OHCI_IRQ (32+1)
|
||||
#define LS1C_OTG_IRQ (32+2)
|
||||
#define LS1C_MAC_IRQ (32+3)
|
||||
#define LS1C_CAM_IRQ (32+4)
|
||||
#define LS1C_UART4_IRQ (32+5)
|
||||
#define LS1C_UART5_IRQ (32+6)
|
||||
#define LS1C_UART6_IRQ (32+7)
|
||||
#define LS1C_UART7_IRQ (32+8)
|
||||
#define LS1C_UART8_IRQ (32+9)
|
||||
#define LS1C_UART9_IRQ (32+13)
|
||||
#define LS1C_UART10_IRQ (32+14)
|
||||
#define LS1C_UART11_IRQ (32+15)
|
||||
#define LS1C_I2C2_IRQ (32+17)
|
||||
#define LS1C_I2C1_IRQ (32+18)
|
||||
#define LS1C_I2C0_IRQ (32+19)
|
||||
|
||||
|
||||
#define LS1C_GPIO_IRQ 64
|
||||
#define LS1C_GPIO_FIRST_IRQ 64
|
||||
#define LS1C_GPIO_IRQ_COUNT 96
|
||||
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
|
||||
|
||||
|
||||
#define LS1C_LAST_IRQ 159
|
||||
#define LS1C_INTREG_BASE 0xbfd01040
|
||||
|
||||
// 将1c的中断分为五组，每组32个
|
||||
#define LS1C_NR_IRQS (32*5)
|
||||
|
||||
|
||||
// GPIO引脚到中断号之间的转换
|
||||
#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn))
|
||||
#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ)
|
||||
|
||||
#endif
|
||||
|
||||
77
RT_Thread/libcpu/mips/gs232/mipscfg.c
Normal file
77
RT_Thread/libcpu/mips/gs232/mipscfg.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-27 swkyer first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <mips.h>
|
||||
|
||||
mips32_core_cfg_t g_mips_core =
|
||||
{
|
||||
16, /* icache_line_size */
|
||||
256, /* icache_lines_per_way */
|
||||
4, /* icache_ways */
|
||||
16, /* dcache_line_size */
|
||||
256, /* dcache_lines_per_way */
|
||||
4, /* dcache_ways */
|
||||
16, /* max_tlb_entries */
|
||||
};
|
||||
|
||||
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
|
||||
{
|
||||
rt_uint16_t rets = 1;
|
||||
|
||||
while (n--)
|
||||
rets *= b;
|
||||
|
||||
return rets;
|
||||
}
|
||||
|
||||
static rt_uint16_t m_log2(rt_uint16_t b)
|
||||
{
|
||||
rt_uint16_t rets = 0;
|
||||
|
||||
while (b != 1)
|
||||
{
|
||||
b /= 2;
|
||||
rets++;
|
||||
}
|
||||
|
||||
return rets;
|
||||
}
|
||||
|
||||
/**
|
||||
* read core attribute
|
||||
*/
|
||||
void mips32_cfg_init(void)
|
||||
{
|
||||
rt_uint16_t val;
|
||||
rt_uint32_t cp0_config1;
|
||||
|
||||
cp0_config1 = read_c0_config();
|
||||
if (cp0_config1 & 0x80000000)
|
||||
{
|
||||
cp0_config1 = read_c0_config1();
|
||||
|
||||
val = (cp0_config1 & (7<<22))>>22;
|
||||
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<19))>>19;
|
||||
g_mips_core.icache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<16))>>16;
|
||||
g_mips_core.icache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (7<<13))>>13;
|
||||
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<10))>>10;
|
||||
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<7))>>7;
|
||||
g_mips_core.dcache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (0x3F<<25))>>25;
|
||||
g_mips_core.max_tlb_entries = val + 1;
|
||||
}
|
||||
}
|
||||
41
RT_Thread/libcpu/mips/gs232/timer.c
Normal file
41
RT_Thread/libcpu/mips/gs232/timer.c
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Assembly Macros For MIPS
|
||||
*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <mips.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*/
|
||||
void rt_hw_timer_handler(void)
|
||||
{
|
||||
unsigned int count;
|
||||
|
||||
count = read_c0_compare();
|
||||
write_c0_compare(count);
|
||||
write_c0_count(0);
|
||||
|
||||
/* increase a OS tick */
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial OS timer
|
||||
*/
|
||||
void rt_hw_timer_init(void)
|
||||
{
|
||||
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
|
||||
write_c0_count(0);
|
||||
mips_unmask_cpu_irq(7);
|
||||
}
|
||||
Reference in New Issue
Block a user