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冯佳
2025-06-19 21:56:46 +08:00
parent fe98e5f010
commit a4841450cf
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13
RT_Thread/libcpu/mips/pic32/SConscript Normal file
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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

136
RT_Thread/libcpu/mips/pic32/context_gcc.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-05-24 aozima first version
* 2019-07-19 Zhou Yanjie clean up code
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <p32xxxx.h>
#include "../common/mips_def.h"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noat
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS /* v0 = status */
addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
mtc0 v1, CP0_STATUS /* status = v1 */
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
/* trigger the soft exception (causes context switch) */
mfc0 t0, CP0_CAUSE /* t0 = Cause */
ori t0, t0, (1<<8) /* t0 |= (1<<8) */
mtc0 t0, CP0_CAUSE /* cause = t0 */
addiu t1, zero, -257 /* t1 = ~(1<<8) */
and t0, t0, t1 /* t0 &= t1 */
mtc0 t0, CP0_CAUSE /* cause = t0 */
jr ra
nop
/*
* void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
*/
.section ".text", "ax"
.set noreorder
.set noat
.ent CoreSW0Handler
.globl CoreSW0Handler
CoreSW0Handler:
SAVE_ALL
/* mCS0ClearIntFlag(); */
la t0, IFS0CLR /* t0 = IFS0CLR */
addiu t1,zero,0x02 /* t1 = (1<<2) */
sw t1, 0(t0) /* IFS0CLR = t1 */
la k0, rt_thread_switch_interrupt_flag
sw zero, 0(k0) /* clear flag */
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
RESTORE_ALL_AND_RET
.end CoreSW0Handler

93
RT_Thread/libcpu/mips/pic32/cpuport.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 20011-05-23 aozima the first version for PIC32.
* 20011-09-05 aozima merge all of C source code into cpuport.c.
*/
#include <rtthread.h>
/**
* @addtogroup PIC32
*/
/*@{*/
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
rt_uint32_t __attribute__((nomips16)) _get_gp(void)
{
rt_uint32_t result;
// get the gp reg
asm volatile("move %0, $28" : "=r"(result));
return result;
}
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */
*(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) 0; /* lo */
*(--stk) = (rt_uint32_t) 0; /* hi */
*(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */
*(--stk) = (rt_uint32_t) texit; /* 31 ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */
*(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */
*(--stk) = (rt_uint32_t) parameter; /* 4 a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */
*(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

98
RT_Thread/libcpu/mips/pic32/exceptions.c Normal file
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/*********************************************************************
*
* Generic Exception Handler
*
*********************************************************************
* FileName: exceptions.c
* Dependencies:
*
* Processor: PIC32
*
* Complier: MPLAB C32
* MPLAB IDE
* Company: Microchip Technology, Inc.
* Author: Darren Wenn
*
* Software License Agreement
*
* The software supplied herewith by Microchip Technology Incorporated
* (the “Company”) for its PIC32/PIC24 Microcontroller is intended
* and supplied to you, the Company’s customer, for use solely and
* exclusively on Microchip PIC32/PIC24 Microcontroller products.
* The software is owned by the Company and/or its supplier, and is
* protected under applicable copyright laws. All rights are reserved.
* Any use in violation of the foregoing restrictions may subject the
* user to criminal sanctions under applicable laws, as well as to
* civil liability for the breach of the terms and conditions of this
* license.
*
* THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
*
********************************************************************/
#include <p32xxxx.h>
// declared static in case exception condition would prevent
// auto variable being created
static enum {
EXCEP_IRQ = 0, // interrupt
EXCEP_AdEL = 4, // address error exception (load or ifetch)
EXCEP_AdES, // address error exception (store)
EXCEP_IBE, // bus error (ifetch)
EXCEP_DBE, // bus error (load/store)
EXCEP_Sys, // syscall
EXCEP_Bp, // breakpoint
EXCEP_RI, // reserved instruction
EXCEP_CpU, // coprocessor unusable
EXCEP_Overflow, // arithmetic overflow
EXCEP_Trap, // trap (possible divide by zero)
EXCEP_IS1 = 16, // implementation specfic 1
EXCEP_CEU, // CorExtend Unuseable
EXCEP_C2E // coprocessor 2
} _excep_code;
static unsigned int _epc_code;
static unsigned int _excep_addr;
#include <rtthread.h>
// this function overrides the normal _weak_ generic handler
void _general_exception_handler(void)
{
asm volatile("mfc0 %0,$13" : "=r" (_excep_code));
asm volatile("mfc0 %0,$14" : "=r" (_excep_addr));
_excep_code = (_excep_code & 0x0000007C) >> 2;
rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
switch(_excep_code)
{
case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
default : rt_kprintf("unkown exception\r\n");break;
}
while (1) {
// Examine _excep_code to identify the type of exception
// Examine _excep_addr to find the address that caused the exception
}
}