原始版本
This commit is contained in:
冯佳
13
RT_Thread/libcpu/ti-dsp/c28x/SConscript
Normal file
13
RT_Thread/libcpu/ti-dsp/c28x/SConscript
Normal file
@ -0,0 +1,13 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.s')
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CPPPATH = [cwd]
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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360
RT_Thread/libcpu/ti-dsp/c28x/context.s
Normal file
360
RT_Thread/libcpu/ti-dsp/c28x/context.s
Normal file
@ -0,0 +1,360 @@
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;
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; Copyright (c) 2006-2022, RT-Thread Development Team
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;
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; SPDX-License-Identifier: Apache-2.0
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;
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; Change Logs:
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; Date Author Notes
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; 2018-09-01 xuzhuoyi the first version.
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; 2019-06-17 zhaoxiaowei fix bugs of old c28x interrupt api.
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; 2019-07-03 zhaoxiaowei add _rt_hw_calc_csb function to support __rt_ffs.
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; 2019-12-05 xiaolifan add support for hardware fpu32
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; 2022-06-21 guyunjie trim pendsv (RTOSINT_Handler)
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; 2022-08-24 guyunjie fix bugs in context switching
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; 2022-10-15 guyunjie add zero-latency interrupt
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.ref rt_interrupt_to_thread
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.ref rt_interrupt_from_thread
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.ref rt_thread_switch_interrupt_flag
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.def rtosint_handler
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.def rt_hw_get_st0
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.def rt_hw_get_st1
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.def rt_hw_calc_csb
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.def rt_hw_context_switch_interrupt
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.def rt_hw_context_switch
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.def rt_hw_context_switch_to
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.def rt_hw_interrupt_thread_switch
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.def rt_hw_interrupt_disable
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.def rt_hw_interrupt_enable
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;importing settings from compiler and config
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.cdecls C,NOLIST
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%{
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#include <rtconfig.h>
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#ifdef __TMS320C28XX_FPU32__
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#define __FPU32__ 1
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#else
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#define __FPU32__ 0
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#endif
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#ifdef __TMS320C28XX_FPU64__
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#define __FPU64__ 1
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#else
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#define __FPU64__ 0
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#endif
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#ifdef __TMS320C28XX_VCRC__
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#define __VCRC__ 1
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#else
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#define __VCRC__ 0
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#endif
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#ifdef RT_USING_ZERO_LATENCY
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#define ZERO_LATENCY 1
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#ifndef ZERO_LATENCY_INT_MASK
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#error ZERO_LATENCY_INT_MASK must be defined for zero latency interrupt
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#elif ZERO_LATENCY_INT_MASK & 0x8000
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#error RTOS bit (0x8000) must not be set in ZERO_LATENCY_INT_MASK
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#endif
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#else
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#define ZERO_LATENCY 0
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#endif
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%}
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.text
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.newblock
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;
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; rt_base_t rt_hw_interrupt_disable();
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;
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.asmfunc
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rt_hw_interrupt_disable:
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.if ZERO_LATENCY
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MOV AL, IER
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AND IER, #ZERO_LATENCY_INT_MASK
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.else
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PUSH ST1
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SETC INTM
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POP AL
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.endif
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MOV AH, #0
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LRETR
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.endasmfunc
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;
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; void rt_hw_interrupt_enable(rt_base_t level);
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;
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.asmfunc
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rt_hw_interrupt_enable:
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.if ZERO_LATENCY
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MOV IER, AL
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.else
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PUSH AL
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POP ST1
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.endif
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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rt_hw_context_switch_interrupt:
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; ACC, XAR4-7 are "save on call" following TI C28x C/C++ compiler convention
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; and therefore can be used in a function without being saved on stack first
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; (the compiler has already saved it before the call).
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; Reference: TMS320C28x Optimizing CC++ Compiler
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; note this convention is only applicable to normal functions not to isrs
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MOVL XAR6, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF reswitch2, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR6
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reswitch2:
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MOVL XAR5, #rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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rt_hw_context_switch:
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MOVL XAR6, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF reswitch1, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR6
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reswitch1:
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MOVL XAR5, #rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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OR IFR, #0x8000
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LRETR
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.endasmfunc
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;
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * ACC --> to
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;
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.asmfunc
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rt_hw_context_switch_to:
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; get to thread
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MOVL XAR5, #rt_interrupt_to_thread
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MOVL *XAR5, ACC
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; set from thread to 0
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MOVL XAR5, #rt_interrupt_from_thread
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MOVL XAR4, #0
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MOVL *XAR5, XAR4
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; set interrupt flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL XAR4, #1
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MOVL *XAR5, XAR4
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; trigger rtos interrupt
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OR IFR, #0x8000
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OR IER, #0x8000
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CLRC INTM
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; never reach here!
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.endasmfunc
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.asmfunc
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rtosint_handler:
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.if ZERO_LATENCY
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; mask out non-critical interrupts and enable global interrupt
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; so rtosint_handler won't block critical interrupts
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AND IER, #ZERO_LATENCY_INT_MASK
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CLRC INTM
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.endif
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MOVL ACC, *-SP[4]
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MOV AR0, AL ; save original IER
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PUSH AR1H:AR0H
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PUSH XAR2
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; get rt_thread_switch_interrupt_flag
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MOVL XAR1, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR1
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BF rtosint_exit, EQ ; rtos_int already handled
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; clear rt_thread_switch_interrupt_flag to 0
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MOVL XAR2, #0
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MOVL *XAR1, XAR2
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MOVL XAR1, #rt_interrupt_from_thread
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MOVL ACC, *XAR1
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BF switch_to_thread, EQ ; skip register save at the first time
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PUSH XAR3
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PUSH XAR4
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PUSH XAR5
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PUSH XAR6
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PUSH XAR7
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PUSH XT
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PUSH RPC
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.if __FPU32__
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PUSH RB
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MOV32 *SP++, STF
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MOV32 *SP++, R0H
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MOV32 *SP++, R1H
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MOV32 *SP++, R2H
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MOV32 *SP++, R3H
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MOV32 *SP++, R4H
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MOV32 *SP++, R5H
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MOV32 *SP++, R6H
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MOV32 *SP++, R7H
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.endif
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.if __FPU64__
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MOV32 *SP++, R0L
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MOV32 *SP++, R1L
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MOV32 *SP++, R2L
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MOV32 *SP++, R3L
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MOV32 *SP++, R4L
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MOV32 *SP++, R5L
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MOV32 *SP++, R6L
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MOV32 *SP++, R7L
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.endif
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.if __VCRC__
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VMOV32 *SP++, VCRC
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VMOV32 *SP++, VSTATUS
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VMOV32 *SP++, VCRCPOLY
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VMOV32 *SP++, VCRCSIZE
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.endif
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||||
MOVL ACC, *XAR1
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MOVL XAR1, ACC
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MOVZ AR2, @SP ; get from thread stack pointer
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MOVL *XAR1, XAR2 ; update from thread stack pointer
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switch_to_thread:
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MOVL XAR1, #rt_interrupt_to_thread
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MOVL ACC, *XAR1
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MOVL XAR1, ACC
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MOVL ACC, *XAR1
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MOV @SP, AL ; load thread stack pointer
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||||
.if __VCRC__
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VMOV32 VCRCSIZE, *--SP
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VMOV32 VCRCPOLY, *--SP
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VMOV32 VSTATUS, *--SP
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||||
VMOV32 VCRC, *--SP
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||||
.endif
|
||||
|
||||
.if __FPU64__
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MOV32 R7L, *--SP
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||||
MOV32 R6L, *--SP
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||||
MOV32 R5L, *--SP
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||||
MOV32 R4L, *--SP
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||||
MOV32 R3L, *--SP
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||||
MOV32 R2L, *--SP
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||||
MOV32 R1L, *--SP
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||||
MOV32 R0L, *--SP
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||||
.endif
|
||||
|
||||
.if __FPU32__
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||||
MOV32 R7H, *--SP
|
||||
MOV32 R6H, *--SP
|
||||
MOV32 R5H, *--SP
|
||||
MOV32 R4H, *--SP
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||||
MOV32 R3H, *--SP
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||||
MOV32 R2H, *--SP
|
||||
MOV32 R1H, *--SP
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||||
MOV32 R0H, *--SP
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||||
MOV32 STF, *--SP
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||||
POP RB
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||||
.endif
|
||||
|
||||
POP RPC
|
||||
POP XT
|
||||
POP XAR7
|
||||
POP XAR6
|
||||
POP XAR5
|
||||
POP XAR4
|
||||
POP XAR3
|
||||
|
||||
rtosint_exit:
|
||||
; do not restore interrupt here: to be restored according to the
|
||||
; switched-to context during IRET (automaticlly by hardware)
|
||||
|
||||
POP XAR2
|
||||
POP AR1H:AR0H
|
||||
|
||||
MOVL ACC , *-SP[4]
|
||||
MOV AL, AR0
|
||||
MOVL *-SP[4], ACC
|
||||
|
||||
IRET
|
||||
.endasmfunc
|
||||
|
||||
.asmfunc
|
||||
rt_hw_get_st0:
|
||||
PUSH ST0
|
||||
POP AL
|
||||
LRETR
|
||||
.endasmfunc
|
||||
|
||||
.asmfunc
|
||||
rt_hw_get_st1:
|
||||
PUSH ST1
|
||||
POP AL
|
||||
LRETR
|
||||
.endasmfunc
|
||||
|
||||
; C28x do not have a build-in "__ffs" func in its C compiler.
|
||||
; We can use the "Count Sign Bits" (CSB) instruction to make one.
|
||||
; CSB will return the number of 0's minus 1 above the highest set bit.
|
||||
; The count is placed in T. For example:
|
||||
; ACC T maxbit
|
||||
; 0x00000001 30 0
|
||||
; 0x00000010 26 4
|
||||
; 0x000001FF 22 8
|
||||
; 0x000001F0 22 8
|
||||
.asmfunc
|
||||
rt_hw_calc_csb:
|
||||
MOV AH, #0
|
||||
CSB ACC ; T = no. of sign bits - 1
|
||||
MOVU ACC, T ; ACC = no. of sign bits - 1
|
||||
SUBB ACC, #30 ; ACC = ACC - 30
|
||||
ABS ACC ; ACC = |ACC|
|
||||
LRETR
|
||||
.endasmfunc
|
||||
|
||||
; compatible with old version
|
||||
.asmfunc
|
||||
rt_hw_interrupt_thread_switch:
|
||||
LRETR
|
||||
NOP
|
||||
.endasmfunc
|
||||
|
||||
.end
|
||||
188
RT_Thread/libcpu/ti-dsp/c28x/cpuport.c
Normal file
188
RT_Thread/libcpu/ti-dsp/c28x/cpuport.c
Normal file
@ -0,0 +1,188 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-09-01 xuzhuoyi the first version.
|
||||
* 2019-07-03 zhaoxiaowei add support for __rt_ffs.
|
||||
* 2019-12-05 xiaolifan add support for hardware fpu32
|
||||
* 2022-10-17 guyunjie add support for hardware fpu64 and vcrc
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
|
||||
#define DBG_TAG "cpu.ti.c28x"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
extern volatile rt_atomic_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
rt_uint32_t rt_interrupt_from_thread;
|
||||
rt_uint32_t rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
/* exception hook */
|
||||
static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
|
||||
|
||||
extern rt_uint16_t rt_hw_get_st0(void);
|
||||
extern rt_uint16_t rt_hw_get_st1(void);
|
||||
extern int rt_hw_calc_csb(int value);
|
||||
|
||||
|
||||
struct exception_stack_frame
|
||||
{
|
||||
rt_uint32_t t_st0;
|
||||
rt_uint32_t acc;
|
||||
rt_uint32_t p;
|
||||
rt_uint32_t ar1_ar0;
|
||||
rt_uint32_t dp_st1;
|
||||
rt_uint32_t dbgstat_ier;
|
||||
rt_uint32_t return_address;
|
||||
};
|
||||
|
||||
struct stack_frame
|
||||
{
|
||||
struct exception_stack_frame exception_stack_frame;
|
||||
|
||||
/* r4 ~ r11 register */
|
||||
rt_uint16_t ar0h;
|
||||
rt_uint16_t ar1h;
|
||||
rt_uint32_t xar2;
|
||||
rt_uint32_t xar3;
|
||||
rt_uint32_t xar4;
|
||||
rt_uint32_t xar5;
|
||||
rt_uint32_t xar6;
|
||||
rt_uint32_t xar7;
|
||||
rt_uint32_t xt;
|
||||
rt_uint32_t rpc;
|
||||
|
||||
#ifdef __TMS320C28XX_FPU32__
|
||||
rt_uint32_t rb;
|
||||
rt_uint32_t stf;
|
||||
rt_uint32_t r0h;
|
||||
rt_uint32_t r1h;
|
||||
rt_uint32_t r2h;
|
||||
rt_uint32_t r3h;
|
||||
rt_uint32_t r4h;
|
||||
rt_uint32_t r5h;
|
||||
rt_uint32_t r6h;
|
||||
rt_uint32_t r7h;
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_FPU64__
|
||||
rt_uint32_t r0l;
|
||||
rt_uint32_t r1l;
|
||||
rt_uint32_t r2l;
|
||||
rt_uint32_t r3l;
|
||||
rt_uint32_t r4l;
|
||||
rt_uint32_t r5l;
|
||||
rt_uint32_t r6l;
|
||||
rt_uint32_t r7l;
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_VCRC__
|
||||
rt_uint32_t vcrc;
|
||||
rt_uint32_t vstatus;
|
||||
rt_uint32_t vcrcpoly;
|
||||
rt_uint32_t vcrcsize;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
void *parameter,
|
||||
rt_uint8_t *stack_addr,
|
||||
void *texit)
|
||||
{
|
||||
struct stack_frame *stack_frame;
|
||||
rt_uint8_t *stk;
|
||||
unsigned long i;
|
||||
|
||||
stk = stack_addr;
|
||||
stk = (rt_uint8_t *)RT_ALIGN((rt_uint32_t)stk, 2);
|
||||
stk += 1; /*to work around the stack alignment*/
|
||||
|
||||
stack_frame = (struct stack_frame *)stk;
|
||||
|
||||
/* zero all registers */
|
||||
for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
|
||||
{
|
||||
((rt_uint32_t *)stack_frame)[i] = 0;
|
||||
}
|
||||
|
||||
/* configure special registers*/
|
||||
stack_frame->exception_stack_frame.dp_st1 = 0x00000A08;
|
||||
stack_frame->xar4 = (rt_uint32_t)parameter;
|
||||
stack_frame->exception_stack_frame.return_address = (rt_uint32_t)tentry;
|
||||
stack_frame->rpc = (rt_uint32_t)texit;
|
||||
|
||||
#ifdef __TMS320C28XX_FPU32__
|
||||
stack_frame->stf = 0x00000200;
|
||||
stack_frame->rb = 0;
|
||||
#endif
|
||||
|
||||
/* return task's current stack address */
|
||||
return stk + sizeof(struct stack_frame);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function set the hook, which is invoked on fault exception handling.
|
||||
*
|
||||
* @param exception_handle the exception handling hook function.
|
||||
*/
|
||||
void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
|
||||
{
|
||||
rt_exception_hook = exception_handle;
|
||||
}
|
||||
|
||||
|
||||
struct exception_info
|
||||
{
|
||||
rt_uint32_t exc_return;
|
||||
struct stack_frame stack_frame;
|
||||
};
|
||||
|
||||
#ifdef RT_USING_CPU_FFS
|
||||
/*
|
||||
* This function called rt_hw_calc_csb to finds the first bit set in value.
|
||||
* rt_hw_calc_csb is a native assembly program that use "CSB" instruction in C28x.
|
||||
* When you use this function, remember that "int" is only 16-bit in C28x's C compiler.
|
||||
* If value is a number bigger that 0xFFFF, trouble may be caused.
|
||||
* Maybe change "int __rt_ffs(int value)" to "rt_int32_t __rt_ffs(rt_int32_t value)" will be better.
|
||||
*/
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
return rt_hw_calc_csb(value);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_interrupt_enter(void)
|
||||
{
|
||||
rt_base_t level;
|
||||
|
||||
__asm(" EINT");
|
||||
level = rt_hw_interrupt_disable();
|
||||
rt_interrupt_nest ++;
|
||||
RT_OBJECT_HOOK_CALL(rt_interrupt_enter_hook,());
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
LOG_D("irq has come..., irq current nest:%d",
|
||||
(rt_int32_t)rt_interrupt_nest);
|
||||
}
|
||||
|
||||
void rt_interrupt_leave(void)
|
||||
{
|
||||
LOG_D("irq is going to leave, irq current nest:%d",
|
||||
(rt_int32_t)rt_interrupt_nest);
|
||||
|
||||
rt_hw_interrupt_disable();
|
||||
RT_OBJECT_HOOK_CALL(rt_interrupt_leave_hook,());
|
||||
rt_interrupt_nest --;
|
||||
if(rt_thread_switch_interrupt_flag && !rt_interrupt_nest)
|
||||
{
|
||||
__asm(" OR IFR, #0x8000"); /* trigger rtos int */
|
||||
}
|
||||
/* rt_hw_interrupt_enable auto done by hardware on IRET */
|
||||
}
|
||||
Reference in New Issue
Block a user